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Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 )
Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Mike, any news here? This change-set is probably not the best way to discuss this. […]
So far I've provided all the requested logs (see above) and tried a suggestion with the "safe" flags (which didn't help unfortunately). This issue have been reproduced by other people with AMD boards like G505S and also Thinkpad X201 ( https://ticket.coreboot.org/issues/322 ) <--- although in X201 case the board seemed unbootable at all, while in my case it usually gets past this coreboot+SeaBIOS point and gets stuck booting Linux. I'm not sure how to proceed, and any suggestions will be appreciated.
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Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/61518/comment/7dfeafb1_ef57f09e
PS1, Line 83: /* Function to set D0I3 for all HECI devices */
: void soc_set_d0i3_for_heci(void)
: {
: unsigned int cse_dev[] = {
: PCH_DEVFN_CSE,
: PCH_DEVFN_CSE_2,
: PCH_DEVFN_CSE_3,
: PCH_DEVFN_CSE_4
: };
:
: for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
: if (!is_cse_devfn_visible(cse_dev[i]))
: continue;
:
: set_cse_device_state(cse_dev[i], DEV_IDLE);
: }
: }
:
> Could this function just be moved to common code?
The only reason why I would prefer to have HECI device lists coming from SoC layer instead common code because of number of HECI device.
ADL, CNL, ICL, JSL, => 4 HECI devices
SKL => 3 HECI devices
TGL => 3 HECI devices (but there is mistake it should be 4 as per EDS)
After reading your comments I had another idea, let me try something today.
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Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
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Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61266/comment/945a40ba_21b2a59a
PS2, Line 10: Hence disabling it.
> Kindly update the tests you did with this CL. […]
Done
https://review.coreboot.org/c/coreboot/+/61266/comment/54f26ac1_31247559
PS2, Line 12: Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
> BUG=b:216533766 […]
Done
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Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Mark Hsieh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61266
to look at the new patch set (#3).
Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
......................................................................
mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.
BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/61266/3
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Change subject: sc7280/qtiseclib blob update
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I got little confused on seeing deltas
last blob was in https://review.coreboot.org/c/qc_blobs/+/59637
so trying to upload based on that gerrit.
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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/61352/comment/9140d373_65890f7f
PS1, Line 53: ext_pm_support
> Done
Tim, ex_pm_support has been changed to use 'enum' type.
- enum type is added in the chip.h
- ex_pm_support is also checked if the methods to request are available or not.
- rtd3 device is also referenced to get its config for this field in the device.
- device calls the exported methods based on ex_pm_support enum.
Please also see the other reviews:
https://review.coreboot.org/c/coreboot/+/61354https://review.coreboot.org/c/coreboot/+/61355
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Change subject: mb/google/guybrush/var/dewatt: Update touchpad GPIO configuration
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/guybrush/variants/dewatt/gpio.c:
https://review.coreboot.org/c/coreboot/+/61174/comment/636a4886_a843b567
PS2, Line 43: LEVEL_LOW
> FW_CONFIG probe is pretty much free isn't it?
It is more to do with the HID over I2C ACPI specification than the trackpad vendor differences.
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered.
http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3…
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