coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61499 ) Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @Tim/Nick/Eric, Can you take a look into this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 08:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "util/crossgcc: Update gcc to 11.2"
by Mike Banon (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Nico Huber, Branden Waldner, Idwer Vollering, Paul Menzel, Jacob Garber, Arthur Heymans, Werner Zeh, Iru Cai, HAOUAS Elyes, Harshit Sharma. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 ) Change subject: Revert "util/crossgcc: Update gcc to 11.2" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Mike, any news here? This change-set is probably not the best way to discuss this. […] So far I've provided all the requested logs (see above) and tried a suggestion with the "safe" flags (which didn't help unfortunately). This issue have been reproduced by other people with AMD boards like G505S and also Thinkpad X201 ( https://ticket.coreboot.org/issues/322 ) <--- although in X201 case the board seemed unbootable at all, while in my case it usually gets past this coreboot+SeaBIOS point and gets stuck booting Linux. I'm not sure how to proceed, and any suggestions will be appreciated. -- To view, visit https://review.coreboot.org/c/coreboot/+/59636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a789f9ccb284ac7cad32b12bbf60ecb82efb44 Gerrit-Change-Number: 59636 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 07:04:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST]src/drivers/intel/fsp2_0: Change fsp_is_multi_phase_init_enable...
by Ronak Kanabar (Code Review) 01 Feb '22

01 Feb '22

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61527 ) Change subject: [TEST]src/drivers/intel/fsp2_0: Change fsp_is_multi_phase_init_enabled check ...................................................................... [TEST]src/drivers/intel/fsp2_0: Change fsp_is_multi_phase_init_enabled check Add check of USE_INTEL_FSP_MP_INIT config in fsp_is_multi_phase_init_enabled Change-Id: I35ba5a3f0540c18652e5ad2c25e11258477e53b6 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/61527/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 83d44b1..cc7a98a 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -75,7 +75,8 @@ bool fsp_is_multi_phase_init_enabled(void) { return CONFIG(FSPS_USE_MULTI_PHASE_INIT) && - (fsps_hdr.multi_phase_si_init_entry_offset != 0); + (fsps_hdr.multi_phase_si_init_entry_offset != 0) && + (!CONFIG(USE_INTEL_FSP_MP_INIT)); } static void fsp_fill_common_arch_params(FSPS_UPD *supd) -- To view, visit https://review.coreboot.org/c/coreboot/+/61527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ba5a3f0540c18652e5ad2c25e11258477e53b6 Gerrit-Change-Number: 61527 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/finalize.c: https://review.coreboot.org/c/coreboot/+/61518/comment/7dfeafb1_ef57f09e PS1, Line 83: /* Function to set D0I3 for all HECI devices */ : void soc_set_d0i3_for_heci(void) : { : unsigned int cse_dev[] = { : PCH_DEVFN_CSE, : PCH_DEVFN_CSE_2, : PCH_DEVFN_CSE_3, : PCH_DEVFN_CSE_4 : }; : : for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) { : if (!is_cse_devfn_visible(cse_dev[i])) : continue; : : set_cse_device_state(cse_dev[i], DEV_IDLE); : } : } : > Could this function just be moved to common code? The only reason why I would prefer to have HECI device lists coming from SoC layer instead common code because of number of HECI device. ADL, CNL, ICL, JSL, => 4 HECI devices SKL => 3 HECI devices TGL => 3 HECI devices (but there is mistake it should be 4 as per EDS) After reading your comments I had another idea, let me try something today. -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 05:51:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
by EricR Lai (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61501 ) Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Gerrit-Change-Number: 61501 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 05:32:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
by EricR Lai (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61500 ) Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 Gerrit-Change-Number: 61500 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 05:32:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
by Meera Ravindranath (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61266 ) Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61266/comment/945a40ba_21b2a59a PS2, Line 10: Hence disabling it. > Kindly update the tests you did with this CL. […] Done https://review.coreboot.org/c/coreboot/+/61266/comment/54f26ac1_31247559 PS2, Line 12: Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> > BUG=b:216533766 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Gerrit-Change-Number: 61266 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 04:37:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
by Meera Ravindranath (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Meera Ravindranath. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Mark Hsieh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61266 to look at the new patch set (#3). Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 ...................................................................... mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 Gimble does not use WWAN and TCP Port 1 according to the schematics. Hence disabling it. BUG=b:216533766 TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/61266/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Gerrit-Change-Number: 61266 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in qc_blobs[master]: sc7280/qtiseclib blob update
by Saurabh Gorecha (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Julius Werner. Saurabh Gorecha has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/61435 ) Change subject: sc7280/qtiseclib blob update ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I got little confused on seeing deltas last blob was in https://review.coreboot.org/c/qc_blobs/+/59637 so trying to upload based on that gerrit. -- To view, visit https://review.coreboot.org/c/qc_blobs/+/61435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I91a04242ab7bdeb2e1f6c112a49d00f05b6a36e2 Gerrit-Change-Number: 61435 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Feb 2022 04:10:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
by Cliff Huang (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Lance Zhao, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61352 ) Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/pcie/rtd3/chip.h: https://review.coreboot.org/c/coreboot/+/61352/comment/9140d373_65890f7f PS1, Line 53: ext_pm_support > Done Tim, ex_pm_support has been changed to use 'enum' type. - enum type is added in the chip.h - ex_pm_support is also checked if the methods to request are available or not. - rtd3 device is also referenced to get its config for this field in the device. - device calls the exported methods based on ex_pm_support enum. Please also see the other reviews: https://review.coreboot.org/c/coreboot/+/61354 https://review.coreboot.org/c/coreboot/+/61355 -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Feb 2022 00:26:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2022