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Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info
......................................................................
Patch Set 3:
(1 comment)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/61521/comment/8fb9800b_20b18b10
PS3, Line 360: rw_space_attributes, NULL, 0);
We will need to set TPMA_NV_AUTHWRITE = 1 to the rw_space_attributes as the tpm_nv_write from PSP fails with an error 0x12F - TPM_RC_AUTH_UNAVAILABLE.
I believe the TPMA_NV_AUTHWRITE needs to be set for the index to be written once the OS has started.
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Change subject: mb/intel/adlrvp: Fix vbt loading error
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Isn't this function being added to ensure we have single binary with different vbt configuration.
@Maulik ?
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Hello build bot (Jenkins), Christian Walter, Angel Pons, Arthur Heymans, Patrick Rudolph, Marvin Drees,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
Configure SATA, USB & HSIO settings per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 34 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/61277/3
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Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/61518/comment/7bf16f7d_24939d82
PS1, Line 83: /* Function to set D0I3 for all HECI devices */
: void soc_set_d0i3_for_heci(void)
: {
: unsigned int cse_dev[] = {
: PCH_DEVFN_CSE,
: PCH_DEVFN_CSE_2,
: PCH_DEVFN_CSE_3,
: PCH_DEVFN_CSE_4
: };
:
: for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
: if (!is_cse_devfn_visible(cse_dev[i]))
: continue;
:
: set_cse_device_state(cse_dev[i], DEV_IDLE);
: }
: }
:
> > Could this function just be moved to common code?
The only reason why I would prefer to have HECI device lists coming from SoC layer instead common code because of number of HECI device.
ADL, CNL, ICL, JSL, TGL => 4 HECI devices
SKL => 3 HECI devices
After reading your comments I had another idea, let me try something today.
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Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/58700/comment/8f0cb853_8c083425
PS2, Line 619: */
> > Patchset #1, #2 have stuff leaking below 0xa0000. […]
CPU 0x1 smbase 9fe00
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Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/prodrive/atlas/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61277/comment/62f700df_95c0f364
PS1, Line 43: PchSerialIoDisabled
> Should be enabled
Done. good catch again :)
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Hello build bot (Jenkins), Christian Walter, Angel Pons, Arthur Heymans, Patrick Rudolph, Marvin Drees,
I'd like you to reexamine a change. Please visit
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Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
Configure SATA, USB & HSIO settings per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 37 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/61277/2
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Subrata Banik has uploaded a new patch set (#32) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/59638 )
Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
FSP 2.3 spec introduced FSP_NON_VOLATILE_STORAGE_HOB2 HOB version
for NV data storage. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated
from FSP 2.3 onwards and is maintained for backward compatibility only.
This patch implements the parsing method for
FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first
searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue
to search for FSP_NON_VOLATILE_STORAGE_HOB HOB.
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/32
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