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Hello build bot (Jenkins), Christian Walter, Angel Pons, Arthur Heymans, Patrick Rudolph, Marvin Drees,
I'd like you to reexamine a change. Please visit
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Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
Configure SATA, USB & HSIO settings per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 34 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/61277/3
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Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/61518/comment/7bf16f7d_24939d82
PS1, Line 83: /* Function to set D0I3 for all HECI devices */
: void soc_set_d0i3_for_heci(void)
: {
: unsigned int cse_dev[] = {
: PCH_DEVFN_CSE,
: PCH_DEVFN_CSE_2,
: PCH_DEVFN_CSE_3,
: PCH_DEVFN_CSE_4
: };
:
: for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
: if (!is_cse_devfn_visible(cse_dev[i]))
: continue;
:
: set_cse_device_state(cse_dev[i], DEV_IDLE);
: }
: }
:
> > Could this function just be moved to common code?
The only reason why I would prefer to have HECI device lists coming from SoC layer instead common code because of number of HECI device.
ADL, CNL, ICL, JSL, TGL => 4 HECI devices
SKL => 3 HECI devices
After reading your comments I had another idea, let me try something today.
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Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/58700/comment/8f0cb853_8c083425
PS2, Line 619: */
> > Patchset #1, #2 have stuff leaking below 0xa0000. […]
CPU 0x1 smbase 9fe00
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Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/prodrive/atlas/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61277/comment/62f700df_95c0f364
PS1, Line 43: PchSerialIoDisabled
> Should be enabled
Done. good catch again :)
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Hello build bot (Jenkins), Christian Walter, Angel Pons, Arthur Heymans, Patrick Rudolph, Marvin Drees,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
Configure SATA, USB & HSIO settings per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 37 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/61277/2
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Subrata Banik has uploaded a new patch set (#32) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/59638 )
Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
FSP 2.3 spec introduced FSP_NON_VOLATILE_STORAGE_HOB2 HOB version
for NV data storage. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated
from FSP 2.3 onwards and is maintained for backward compatibility only.
This patch implements the parsing method for
FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first
searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue
to search for FSP_NON_VOLATILE_STORAGE_HOB HOB.
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/32
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Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
Patch Set 18:
(4 comments)
Patchset:
PS15:
> Just to make sure we're still on the same page, you're aware that all the other patches for this eff […]
Done
File payloads/libpayload/include/mem_chip_info.h:
https://review.coreboot.org/c/coreboot/+/59193/comment/2582a737_96401d5a
PS15, Line 44: } dram_info;
> Please create a header in coreboot/src/commonlib/bsd/include/commonlib/bsd/ for this structure, so t […]
Done
File payloads/libpayload/include/mem_chip_info.h:
https://review.coreboot.org/c/coreboot/+/59193/comment/3becdc1c_e112ff88
PS11, Line 44: }dram_info;
> Fixed in next update.
Done
File payloads/libpayload/libc/coreboot.c:
https://review.coreboot.org/c/coreboot/+/59193/comment/1371a413_daf53023
PS15, Line 263: case CB_TAG_MEM_CHIP_INFO:
> This needs to be a CBMEM_ID, not a CB_TAG. […]
Done
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Change subject: soc/qualcomm/common: Add dram information to CBMEM table
......................................................................
Patch Set 18:
(11 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59195/comment/c3bb36e2_8fa9658a
PS1, Line 7: Added
> Add
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/59195/comment/e2ddcb70_92ef9ddb
PS6, Line 7: soc
> soc/qualcomm/common
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/59195/comment/270ce996_a3edc0a0
PS8, Line 7: Added
> Please use imperative mood (present): Add.
Done
https://review.coreboot.org/c/coreboot/+/59195/comment/4ba87986_f748f961
PS8, Line 7: cbmem
> CBMEM table(?)
Done
https://review.coreboot.org/c/coreboot/+/59195/comment/c29832b6_c5036877
PS8, Line 7: soc
> Which one? […]
Done
https://review.coreboot.org/c/coreboot/+/59195/comment/33d4f817_ac07e9ad
PS8, Line 10: TEST=Validated on qualcomm sc7280 developement board
> How exactly?
structure entries tested through proc interface(HLOS). Please find below logs.
localhost ~ # ls -lrt /proc/device-tree/firmware/memchipinfo/
total 0
-r--r--r--. 1 root root 4 Oct 20 16:55 revision_id
-r--r--r--. 1 root root 12 Oct 20 16:55 name
-r--r--r--. 1 root root 4 Oct 20 16:55 io_width
-r--r--r--. 1 root root 4 Oct 20 16:55 density
-r--r--r--. 1 root root 12 Oct 20 16:55 compatible
-r--r--r--. 1 root root 16 Oct 20 16:55 reg
-r--r--r--. 1 root root 4 Oct 20 16:55 manufacturer_id
localhost ~ #
Commit Message:
https://review.coreboot.org/c/coreboot/+/59195/comment/7ffea020_853f600a
PS16, Line 9: BUG=b:182963902
> Please add Bug id 177917361, to BUG=
Done
File src/soc/qualcomm/common/include/soc/mmu_common.h:
https://review.coreboot.org/c/coreboot/+/59195/comment/1ea3ffe6_5bf45951
PS3, Line 13: static struct region * const ddr_region = (struct region *)_ddr_information;
> We will removew once mem_chip_info is squared away, this is temporarily on hold.
Done
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/59195/comment/f5ac0849_147af8fc
PS5, Line 26: static void write_mem_chip_information(struct qclib_cb_if_table_entry *te);
> static functions don't need a prototype.
Done
https://review.coreboot.org/c/coreboot/+/59195/comment/7ca18747_3d5a0f4e
PS5, Line 37:
> There should be some kind of check here to make sure the data was actually filled out (e.g. […]
Done
https://review.coreboot.org/c/coreboot/+/59195/comment/0f289d4a_513f7821
PS5, Line 40: ASSERT(mem_region_base != NULL);
> nit: can just write […]
Done
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