coreboot-gerrit February 2022

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Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Paul Menzel, Thejaswani Putta. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... Patch Set 8: (3 comments) File src/drivers/wwan/fm/acpi_fm350gl.c: https://review.coreboot.org/c/coreboot/+/61354/comment/b7567941_aa238297 PS7, Line 55: acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); : if (wwan_fm350gl_get_rtd3_method_support(config) | ACPI_PCIE_RP_EMIT_L23) : acpigen_emit_namestring(acpi_device_path_join(parent_dev, "DL23")); : /* assert PERST# pin */ : acpigen_enable_tx_gpio(&config->perst_gpio); Sorry am I misreading the logic here? I am reading this as: If PERST# is low, run the DL23() Method and then drive PERST# low? even though the TX state already was read back as low? https://review.coreboot.org/c/coreboot/+/61354/comment/3e09a204_33905000 PS7, Line 64: /* warm reset */ : acpigen_write_if_lequal_op_int(ARG0_OP, 0); : acpigen_write_sleep(FM350GL_TBTG); : /* cold reset */ : acpigen_write_else(); : acpigen_write_if_lequal_op_int(ARG0_OP, 1); suggestion: add some macros here like ``` enum reset_type { RESET_TYPE_WARM = 0, RESET_TYPE_COLD = 1, }; ``` and then you can use those directly here https://review.coreboot.org/c/coreboot/+/61354/comment/76b26178_720e3878 PS7, Line 52: acpigen_write_method_serialized("FHRF", 1); : /* LOCAL0 = PERST# */ : acpigen_get_tx_gpio(&config->perst_gpio); : acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); : if (wwan_fm350gl_get_rtd3_method_support(config) | ACPI_PCIE_RP_EMIT_L23) : acpigen_emit_namestring(acpi_device_path_join(parent_dev, "DL23")); : /* assert PERST# pin */ : acpigen_enable_tx_gpio(&config->perst_gpio); : acpigen_write_if_end(); /* If */ : acpigen_write_sleep(FM350GL_TR2B); : /* assert RESET# pin */ : acpigen_enable_tx_gpio(&config->reset_gpio); : /* warm reset */ : acpigen_write_if_lequal_op_int(ARG0_OP, 0); : acpigen_write_sleep(FM350GL_TBTG); : /* cold reset */ : acpigen_write_else(); : acpigen_write_if_lequal_op_int(ARG0_OP, 1); : /* disable source clock */ : if (wwan_fm350gl_get_rtd3_method_support(config) | ACPI_PCIE_RP_EMIT_SRCK) : acpigen_emit_namestring(acpi_device_path_join(parent_dev, "SRCK")); : acpigen_emit_byte(ZERO_OP); : acpigen_write_sleep(FM350GL_TB2F); : /* assert FCPO# pin */ : acpigen_enable_tx_gpio(&config->fcpo_gpio); : acpigen_write_sleep(FM350GL_TFDI); : acpigen_write_if_end(); /* If */ : acpigen_pop_len(); /* Else */ : acpigen_write_method_end(); /* Method */ : } suggestion: To make the If scopes and nesting read more like C, we can use arbitrary nested scopes in the actual C code to make it read similarly, e.g. ``` { acpigen_write_method_serialized("FHRF", 1); /* LOCAL0 = PERST# */ acpigen_get_tx_gpio(&config->perst_gpio); acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); { if (wwan_fm350gl_get_rtd3_method_support(config) | ACPI_PCIE_RP_EMIT_L23) acpigen_emit_namestring(acpi_device_path_join(parent_dev, "DL23")); /* assert PERST# pin */ acpigen_enable_tx_gpio(&config->perst_gpio); } acpigen_write_if_end(); /* If */ acpigen_write_sleep(FM350GL_TR2B); /* assert RESET# pin */ acpigen_enable_tx_gpio(&config->reset_gpio); acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_WARM); { acpigen_write_sleep(FM350GL_TBTG); } acpigen_write_else(); { acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_COLD); { /* disable source clock */ if (wwan_fm350gl_get_rtd3_method_support(config) | ACPI_PCIE_RP_EMIT_SRCK) acpigen_emit_namestring(acpi_device_path_join(parent_dev, "SRCK")); acpigen_emit_byte(ZERO_OP); acpigen_write_sleep(FM350GL_TB2F); /* assert FCPO# pin */ acpigen_enable_tx_gpio(&config->fcpo_gpio); acpigen_write_sleep(FM350GL_TFDI); } acpigen_write_if_end(); /* If */ } acpigen_pop_len(); /* Else */ acpigen_write_method_end(); /* Method */ } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 17:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used table
by Martin Roth (Code Review) 03 Feb '22

03 Feb '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61452 ) Change subject: mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used table ...................................................................... mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used table With the APCB edit tool enabled in commit 6a3ecc5 (guybrush: Inject SPDs into APCB), DeWatt and Nipperkin can have independent mem_parts_used tables. Copied common table from guybrush and ran part_id_gen to make sure it's synced to latest. BUG=b:209486191 BRANCH=guybrush TEST=Boot on nipperkin Change-Id: Id30b596c2466902dfcc59dcc88dcaa00748a3949 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61452 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc M src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt A src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc M src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt M src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc M src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt A src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt 8 files changed, 37 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 313feb5..02eafcb 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index dfd1aac..d574a6f 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt new file mode 100644 index 0000000..298e58b --- /dev/null +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt @@ -0,0 +1,14 @@ +MT53E1G32D2NP-046 WT:A +MT53E512M32D2NP-046 WT:F +NT6AP256T32AV-J1 +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:B +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc index 9c40489..2b86d00 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc @@ -7,4 +7,4 @@ SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt index 44c16e9..ed9ee86 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt @@ -16,3 +16,5 @@ K4U6E3S4AB-MGCL 1 (0001) H54G46CYRBX267 1 (0001) MT53E512M32D1NP-046 WT:B 1 (0001) +H54G56CYRBX247 3 (0011) +K4UBE3D4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc index bf8462d..9becda6 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247 +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt index 3c38550..f85255d 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -17,3 +17,4 @@ H54G46CYRBX267 1 (0001) MT53E512M32D1NP-046 WT:B 1 (0001) H54G56CYRBX247 3 (0011) +K4UBE3D4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt new file mode 100644 index 0000000..298e58b --- /dev/null +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt @@ -0,0 +1,14 @@ +MT53E1G32D2NP-046 WT:A +MT53E512M32D2NP-046 WT:F +NT6AP256T32AV-J1 +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:B +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B +H54G56CYRBX247 +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/61452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id30b596c2466902dfcc59dcc88dcaa00748a3949 Gerrit-Change-Number: 61452 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Martin Roth (Code Review) 03 Feb '22

03 Feb '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61532 ) Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... soc/intel/apollolake: Rename PWRMBASE macro and function This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is aligned with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61532 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 6 files changed, 12 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 7611a2d..b41a21a 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -30,7 +30,7 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PMC_BAR0, IBAS) + Store (PCH_PWRM_BASE_ADDRESS, IBAS) CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 14e9b11..fe0cb93 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -62,7 +62,7 @@ pci_devfn_t pmc = PCH_DEV_PMC; /* Set PMC base addresses and enable decoding. */ - pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS); pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 5e5b40e..e92227b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,7 +25,7 @@ #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) /* Accesses to these BARs are hardcoded in FSP */ -#define PMC_BAR0 0xfe042000 +#define PCH_PWRM_BASE_ADDRESS 0xfe042000 #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index bc50b87..01efaff 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -235,6 +235,9 @@ void pch_log_state(void); +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 959fb53..4bb6229 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -15,7 +15,7 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg) { cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0; - cfg->pwrmbase_addr = PMC_BAR0; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; cfg->pwrmbase_size = PMC_BAR0_SIZE; cfg->abase_offset = PCI_BASE_ADDRESS_4; cfg->abase_addr = ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 06c2d63..fbb2345 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -24,14 +24,14 @@ #include "chip.h" -static uintptr_t read_pmc_mmio_bar(void) +uint8_t *pmc_mmio_regs(void) { - return PMC_BAR0; + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; } uintptr_t soc_read_pmc_base(void) { - return read_pmc_mmio_bar(); + return (uintptr_t)pmc_mmio_regs(); } uint32_t *soc_pmc_etr_addr(void) @@ -153,7 +153,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) { - uintptr_t pmc_bar0 = read_pmc_mmio_bar(); + uintptr_t pmc_bar0 = soc_read_pmc_base(); ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); @@ -200,7 +200,7 @@ int vbnv_cmos_failed(void) { - uintptr_t pmc_bar = read_pmc_mmio_bar(); + uintptr_t pmc_bar = soc_read_pmc_base(); uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); int rtc_failure = rtc_failed(gen_pmcon1); 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by HAOUAS Elyes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61533 ) Change subject: [only for test] test gcc-12 snapshot ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: it will fail as I've removed -Wno-array-bounds flag -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 17:06:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by HAOUAS Elyes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth. HAOUAS Elyes has removed Julius Werner from this change. ( https://review.coreboot.org/c/coreboot/+/61533 ) Change subject: [only for test] test gcc-12 snapshot ...................................................................... Removed reviewer Julius Werner. -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: herobrine: update SPI-NOR config options
by Sudheer Amrabadi (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Sajida Bhanu, Sudheer Amrabadi, mturney mturney. Sudheer Amrabadi has uploaded a new patch set (#7) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/61279 ) Change subject: herobrine: update SPI-NOR config options ...................................................................... herobrine: update SPI-NOR config options Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan(a)quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Signed-off-by: T Michael Turney <quic_mturney(a)quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/61279/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Gerrit-Change-Number: 61279 Gerrit-PatchSet: 7 Gerrit-Owner: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Reviewer: Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Specify Build Directory
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61572 ) Change subject: payloads/tianocore: Specify Build Directory ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61572/comment/f6de4f05_f6abbd98 PS1, Line 9: Pass build directory of `Build/coreboot` so all variants will output to the > reflow to < 75 characters? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I055f7fb13c7b5f7f1703230e329160da2ef3f137 Gerrit-Change-Number: 61572 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 17:00:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Specify Build Directory
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Sean Rhodes, Matt DeVillier, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61572 to look at the new patch set (#2). Change subject: payloads/tianocore: Specify Build Directory ...................................................................... payloads/tianocore: Specify Build Directory Pass build directory of `Build/coreboot` so all variants will output to the same directory. This only makes the Makefile simpler. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I055f7fb13c7b5f7f1703230e329160da2ef3f137 --- M payloads/external/tianocore/Makefile 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/61572/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I055f7fb13c7b5f7f1703230e329160da2ef3f137 Gerrit-Change-Number: 61572 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/haswell: Report SMBIOS memory speed in MT/s
by HAOUAS Elyes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61504 ) Change subject: nb/intel/haswell: Report SMBIOS memory speed in MT/s ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Gerrit-Change-Number: 61504 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:56:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth, Andy Pont, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 8: (6 comments) File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/61550/comment/f04cc42f_4803b270 PS8, Line 9: config TIANOCORE_REPOSITORY : string "URL to git repository for edk2" : default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM : default "https://github.com/mrchromebox/edk2" > I think this should default to "https://review.coreboot. […] I would agree - but in the future as coreboot's fork hasn't really got anything useful in it. I'm in the process of cleaning/re-writing/upstreaming the edk2 patches, it's slow going, hopefully in a month or so I can propose to reset coreboot's fork to upstream. https://review.coreboot.org/c/coreboot/+/61550/comment/a5c95d2c_6f522921 PS8, Line 14: TIANOCORE_TAG > since this doesn't need to be a tag, maybe TIANOCORE_TAG_OR_REV ? Done https://review.coreboot.org/c/coreboot/+/61550/comment/612f694d_a11e13f8 PS8, Line 82: Disabling this option, which will reserve memory above 4G, > I think this could be phrased better - Though it's probable that nobody will misunderstand, It seems […] Done https://review.coreboot.org/c/coreboot/+/61550/comment/d31ebcee_49578813 PS8, Line 128: without an internal > with an external display? Done https://review.coreboot.org/c/coreboot/+/61550/comment/d94cc41b_a4f1c733 PS8, Line 136: by ~220KB. > This will probably change in the future, so maybe say something like "as of Jan 2022, this increases […] I've changed it as it's wrong - Matt's branch is hardcoded to 0x800000 and nothing you do will get close to that limit. The tidied patch adds 0x10000 as that's all that is needed. File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61550/comment/c99d80a0_72c16e8b PS8, Line 26: -D A > Nit: I think we usually prefer to have -D options without the space. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:55:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2022