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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base
......................................................................
soc/intel/graphics: Create Kconfig for shifting graphic memory base
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to shift graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in KConfig under soc folder.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/15
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Change subject: payloads/external/GRUB2: make modules configurable
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Needs to be rebased, but let's get this merged if it still makes sense.
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Change subject: payloads/tianocore: Rework Makefile
......................................................................
Patch Set 8:
(6 comments)
File payloads/external/tianocore/Kconfig:
https://review.coreboot.org/c/coreboot/+/61550/comment/f490f9d2_4c2a5df2
PS8, Line 9: config TIANOCORE_REPOSITORY
: string "URL to git repository for edk2"
: default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM
: default "https://github.com/mrchromebox/edk2"
I think this should default to "https://review.coreboot.org/edk2", which should in theory be a superset of the mrchromebox repo.
https://review.coreboot.org/c/coreboot/+/61550/comment/9c8ea935_2c60fd8f
PS8, Line 14: TIANOCORE_TAG
since this doesn't need to be a tag, maybe TIANOCORE_TAG_OR_REV ?
https://review.coreboot.org/c/coreboot/+/61550/comment/d8119693_a6b23b06
PS8, Line 82: Disabling this option, which will reserve memory above 4G,
I think this could be phrased better - Though it's probable that nobody will misunderstand, It seems to be saying that disabling the option will enable the memory above 4G.
maybe "Disabling memory above 4G is useful..."
https://review.coreboot.org/c/coreboot/+/61550/comment/4976f313_48eb7d36
PS8, Line 128: without an internal
with an external display?
https://review.coreboot.org/c/coreboot/+/61550/comment/cafd8529_a9edcc83
PS8, Line 136: by ~220KB.
This will probably change in the future, so maybe say something like "as of Jan 2022, this increases..."
File payloads/external/tianocore/Makefile:
https://review.coreboot.org/c/coreboot/+/61550/comment/f86e5aee_ebe8a030
PS8, Line 26: -D A
Nit: I think we usually prefer to have -D options without the space. I don't think it's particularly important, and I see that it wasn't that way in the old makefile, but I thought I'd mention it.
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Change subject: amdfwtool: Add SPL support
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/cezanne: Add the fw SPL to fw.cfg
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/guybrush: Add the fw SPL to amdfw.cfg
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg:
https://review.coreboot.org/c/coreboot/+/61445/comment/3ceb6262_ef69aafc
PS1, Line 27: TypeId0x55_SplTable_Prod_CZN_Chrome
> Not sure this is required upstream. […]
I think we should push it upstream at some point. Ideally we should be able to build functional firmware from the upstream repos.
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/2187e44f_503e44cf
PS6, Line 30: #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(3)
This should be BIT(12). PSP sets bit 12 to indicate fusing is required.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61266 )
Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
......................................................................
mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.
BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
Sridhar Siricilla: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 23071fe..408d380 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -38,6 +38,7 @@
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+ register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -121,6 +122,7 @@
device generic 0 on end
end
end
+ device ref pcie_rp6 off end
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61296 )
Change subject: mb/prodrive/atlas: Configure PCIe device tree settings
......................................................................
mb/prodrive/atlas: Configure PCIe device tree settings
Add CPU & PCH PCIe configs and remove the unused devices.
Configures per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 36 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index ccda650..7b094e4 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -41,29 +41,56 @@
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80)
+ # Clock source is shared hence marked as free running.
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(7)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(10)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
+ register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
+
+ # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
+ # Clock source is shared hence marked as free running.
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "cpu_pcie_rp[CPU_RP(2)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "cpu_pcie_rp[CPU_RP(3)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+
device domain 0 on
device ref pcie5 on end
device ref igpu on end
device ref dtt on end
device ref pcie4_0 on end
device ref pcie4_1 on end
- device ref tbt_pcie_rp0 on end
- device ref tbt_pcie_rp1 on end
- device ref tbt_pcie_rp2 on end
- device ref tbt_pcie_rp3 on end
device ref crashlog off end
device ref xhci on end
- device ref cnvi_wifi on end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp1 on end
- device ref pcie_rp3 on end # W/A to FSP issue
- device ref pcie_rp4 on end # W/A to FSP issue
device ref pcie_rp5 on end
device ref pcie_rp6 on end
device ref pcie_rp8 on end
device ref pcie_rp9 on end
- device ref pcie_rp11 on end
+ device ref pcie_rp10 on end
device ref uart0 on end
device ref uart1 on end
device ref p2sb on end
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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