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Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1
......................................................................
soc/intel/tigerlake: Use PMC IPC to disable HECI1
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Tiger Lake to disable HECI1 device using PMC IPC.
Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/tigerlake/smihandler.c
3 files changed, 3 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/6
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1
......................................................................
soc/intel/alderlake: Use PMC IPC to disable HECI1
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Alder Lake to disable HECI1 device using PMC IPC.
Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/alderlake/smihandler.c
3 files changed, 3 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61458/5
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Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
soc/intel/{adl, common}: Add routines into CSE IA-common code
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3 => Set CSE device state to D0I3
- heci_set_to_d0i3 => Function sets D0I3 for all HECI devices
Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.
As per PCH EDS, the HECI device count for various SoCs are:
ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL => 1 (CSE)
SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3)
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
---
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/skylake/Kconfig
M src/soc/intel/xeon_sp/Kconfig
7 files changed, 43 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/61518/2
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Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
......................................................................
soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
This patch creates a global function `cse_send_end_of_post()` so
that IA common code may get access to this function for sending EOP
command to the HECI1/CSE device.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc
---
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61519/2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
......................................................................
soc/intel/common/cse: Add function to perform CSE lock configuration
This patch implements `cse_lock_config()` to perform the required CSE
lock configuration as per ME BWG (doc: 627331).
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61520/2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
soc/intel/common/block/notify: Implement coreboot notify native driver
This patch implements the required HECI operations to perform prior
to booting to OS after platform decides to skip FSP notify APIs
i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_NOTIFY:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
A src/soc/intel/common/block/notify/Kconfig
A src/soc/intel/common/block/notify/Makefile.inc
A src/soc/intel/common/block/notify/notify.c
3 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/17
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs
......................................................................
soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs
SoC selects `SOC_INTEL_COMMON_BLOCK_NOTIFY` Kconfig to skip FSP notify
APIs (Ready to boot and End of Firmware) and make use of native coreboot
driver to perform require heci notify prior booting to OS.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_NOTIFY.
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
2 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/60406/12
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 )
Change subject: soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/61519/comment/2e5ebb3b_0b402a46
PS1, Line 496: send_end_of_post_to_cse
> suggestion: […]
Ack
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 )
Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/61518/comment/cf1e3b88_44219363
PS1, Line 83: /* Function to set D0I3 for all HECI devices */
: void soc_set_d0i3_for_heci(void)
: {
: unsigned int cse_dev[] = {
: PCH_DEVFN_CSE,
: PCH_DEVFN_CSE_2,
: PCH_DEVFN_CSE_3,
: PCH_DEVFN_CSE_4
: };
:
: for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
: if (!is_cse_devfn_visible(cse_dev[i]))
: continue;
:
: set_cse_device_state(cse_dev[i], DEV_IDLE);
: }
: }
:
> > > Could this function just be moved to common code? […]
Ack
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