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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/61352/comment/41450615_d9e205b4
PS5, Line 9: ACPI_PCIE_RP_EMIT_NONE = 0x00, /* None */
: ACPI_PCIE_RP_EMIT_L23 = 0x01, /* L23 */
: ACPI_PCIE_RP_EMIT_PSD0 = 0x02, /* PSD0 */
: ACPI_PCIE_RP_EMIT_SRCK = 0x04, /* SRCK */
: ACPI_PCIE_RP_EMIT_L23_PSD0 = 0x03, /* L23, PSD0 */
: ACPI_PCIE_RP_EMIT_L23_SRCK = 0x05, /* L23, SRCK */
: ACPI_PCIE_RP_EMIT_PSD0_SRCK = 0x06, /* PSD0, SRCK */
: ACPI_PCIE_RP_EMIT_ALL = 0x07 /* L23, PSD0, SRCK */
: };
Since we don't want the default behavior of this driver to change, ACPI_PCIE_RP_EMIT_ALL should be `0`, because boards that do not set `ext_pm_support` (i.e., all the current boards) still need those Methods defined for where this driver is currently used.
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Change subject: mb/google/brya: Update Type-C USB2 port configuration
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Change subject: [only for test] test gcc-12 snapshot
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Patch Set 3:
(1 comment)
Patchset:
PS3:
Looks like it's failing on the ADA build:
https://qa.coreboot.org/job/coreboot-toolchain/1138/artifact/util/crossgcc/…
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Change subject: [TESTME] soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUS
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Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55430/comment/9da593fa_13246975
PS5, Line 10: talk to each other via PCI, there is no longer the requirement that the
s/PCI/system bus (does AMD call anything FSB?)
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Change subject: soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA
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Change subject: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODO
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Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMU
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
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Patch Set 6:
(1 comment)
Patchset:
PS2:
> This was not related to X2APIC_ONLY choice problem.
CB:60213 solved X2APIC_ONLY for me with denverton_ns
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
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Patch Set 6:
(2 comments)
File src/cpu/x86/smm/smm_stub.S:
https://review.coreboot.org/c/coreboot/+/58386/comment/0507d036_303a6fa0
PS4, Line 108: jc 1f
> the carry flag and zero flag are set as if `%eax - $0xb` is performed, so if the highest leaf is < 0 […]
Ack
https://review.coreboot.org/c/coreboot/+/58386/comment/6141b606_a1e2c523
PS4, Line 124: cmp (%ebx, %ecx, 2), %ax
> This is an idea for a follow-up, right?
Ack
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