Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61503 )
Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> > > Have we decided that the SoC will no longer manually lock gpios it deems sensitive, and instead […]
I think putting the responsibility of locking (or not locking) gpios onto the motherboard is fine (since we're not trying to protect from someone opening up the DUT and connecting up HW to hack in, it seems silly to lock gpios that could be NCs on a DUT, which is what the soc_lock_gpios() currently does).
Thanks for this work, you're making lots of good changes.
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Change subject: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
PS1:
Can you please add a comment to the commit message to make it clear that it is now the responsibility of the mainboard to lock all sensitive GPIOs?
https://review.coreboot.org/c/coreboot/+/61588/comment/53a8b667_03001f43
PS1, Line 15: built
NIT - build
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Change subject: soc/intel/common: Remove GPIO PAD lock config override from mainboard
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61587/comment/6af90407_b18f8eb3
PS2, Line 15: built
NIT - build
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Change subject: soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA
......................................................................
Patch Set 2: Code-Review+2
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Change subject: src/ec: Get rid of unnecessary blank line {before,after} brace
......................................................................
Patch Set 2: Code-Review+2
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Hello Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61601
to look at the new patch set (#2).
Change subject: soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA
......................................................................
soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA
Sabrina has no SATA controller, so remove the corresponding PIRQ
mapping. This was verified with PPR #57243 Rev 1.53.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85
---
M src/mainboard/amd/chausie/mainboard.c
M src/soc/amd/sabrina/fch.c
M src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h
3 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/61601/2
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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 )
Change subject: mb/google/brya: Update Type-C USB2 port configuration
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/61352/comment/41450615_d9e205b4
PS5, Line 9: ACPI_PCIE_RP_EMIT_NONE = 0x00, /* None */
: ACPI_PCIE_RP_EMIT_L23 = 0x01, /* L23 */
: ACPI_PCIE_RP_EMIT_PSD0 = 0x02, /* PSD0 */
: ACPI_PCIE_RP_EMIT_SRCK = 0x04, /* SRCK */
: ACPI_PCIE_RP_EMIT_L23_PSD0 = 0x03, /* L23, PSD0 */
: ACPI_PCIE_RP_EMIT_L23_SRCK = 0x05, /* L23, SRCK */
: ACPI_PCIE_RP_EMIT_PSD0_SRCK = 0x06, /* PSD0, SRCK */
: ACPI_PCIE_RP_EMIT_ALL = 0x07 /* L23, PSD0, SRCK */
: };
Since we don't want the default behavior of this driver to change, ACPI_PCIE_RP_EMIT_ALL should be `0`, because boards that do not set `ext_pm_support` (i.e., all the current boards) still need those Methods defined for where this driver is currently used.
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Change subject: mb/google/brya: Update Type-C USB2 port configuration
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61533 )
Change subject: [only for test] test gcc-12 snapshot
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Looks like it's failing on the ADA build:
https://qa.coreboot.org/job/coreboot-toolchain/1138/artifact/util/crossgcc/…
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