coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

1 participants
7066 discussions

Change in coreboot[master]: cpu/x86/lapic: Add lapic_send_ipi_self,others()
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60713 ) Change subject: cpu/x86/lapic: Add lapic_send_ipi_self,others() ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Gerrit-Change-Number: 60713 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:53:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Wonkyu Kim, Angel Pons, Kyösti Mälkki, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58386 ) Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1f46fe5091ebeab6dfb4c7e151150cf495d0cb Gerrit-Change-Number: 58386 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:52:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Update Type-C USB2 port configuration
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Maulik V Vaghela, Ravindra, Sridhar Siricilla, Mark Hsieh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 ) Change subject: mb/google/brya: Update Type-C USB2 port configuration ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/include/soc/usb.h: PS4: Can we please split out the mainboard changes from the SoC changes? -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:50:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add CPU Crashlog PCI driver
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Francois Toguo Fotso, Furquan Shaikh, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57685 ) Change subject: soc/intel/common: Add CPU Crashlog PCI driver ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/crashlog/cpu_crashlog.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139924): https://review.coreboot.org/c/coreboot/+/57685/comment/85d9da82_6bac32c0 PS7, Line 173: printk(BIOS_SPEW, "Collecting %u dwords from SRAM at %lx\n", buffer.size, bar + buffer.offset); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139924): https://review.coreboot.org/c/coreboot/+/57685/comment/767737e8_74e24ad8 PS7, Line 186: header_offset = crashlog_info.table.offset + offsetof(struct cpu_crashlog_table, header); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cb61fa2570adcfe51680141ee12e0e83930bb19 Gerrit-Change-Number: 57685 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:49:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add crashlog records to BERT
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Francois Toguo Fotso, Furquan Shaikh, Nick Vaccaro, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57686 ) Change subject: soc/intel/common: Add crashlog records to BERT ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/common/block/acpi/acpi_bert.c: https://review.coreboot.org/c/coreboot/+/57686/comment/35d9d684_bfcabdb4 PS3, Line 34: if (cpu_entry) > This check isn't needed, it's covered on line 24. Done https://review.coreboot.org/c/coreboot/+/57686/comment/a234931b_9af54994 PS3, Line 52: if (pmc_entry) > This check isn't needed, it's covered on line 24. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I646053e00fbe4649d5fdcc7ae91dfa8477a5ae65 Gerrit-Change-Number: 57686 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:49:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add PMC Crashlog PCI driver
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Furquan Shaikh, Francois Toguo Fotso, Subrata Banik, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57684 ) Change subject: soc/intel/common: Add PMC Crashlog PCI driver ...................................................................... Patch Set 7: (9 comments) File src/soc/intel/common/block/crashlog/Kconfig: https://review.coreboot.org/c/coreboot/+/57684/comment/960eed18_145b8be7 PS6, Line 4: Enables crashlog PCI drivers which collect crashlog data on boot, > I believe more than SoC, there should be a flexibility given to mainboards or platform users to choo […] Done https://review.coreboot.org/c/coreboot/+/57684/comment/2eb5c5ac_37aaf61a PS6, Line 8: SOC_INTEL_COMMON_BLOCK_CRASHLOG_PMC_TRIGGER_ON_RESET > WDYT about this name, do the Kconfig need to be explicit about whether PMC is the one who is trigger […] Done https://review.coreboot.org/c/coreboot/+/57684/comment/0c118ac6_9afcc8d9 PS6, Line 17: SOC_INTEL_COMMON_BLOCK_CRASHLOG_DISABLE > Ideally yes, knowing the this PCI device has two major purpose. […] SG File src/soc/intel/common/block/crashlog/pmc_crashlog.c: https://review.coreboot.org/c/coreboot/+/57684/comment/ad8ad8ce_dbb2bfd1 PS6, Line 30: discovery_response > Why is this here and not in crashlog_lib. […] Done https://review.coreboot.org/c/coreboot/+/57684/comment/88c90bc4_821603c6 PS6, Line 53: bool crashlog_copy_pmc_records(void *dest, size_t size) : { : const struct cbmem_entry *entry; : : entry = cbmem_entry_find(CBMEM_ID_PMC_CRASHLOG); : if (!entry || !cbmem_entry_size(entry)) : return false; : : memcpy(dest, cbmem_entry_start(entry), MIN(size, cbmem_entry_size(entry))); : : return true; : } > Is this function really required? The caller is already making calls to `cbmem_entry_find()` and `cb […] Ack https://review.coreboot.org/c/coreboot/+/57684/comment/b6f42ec7_b5b34824 PS6, Line 72: if (res == NULL) : res = &placeholder; > Not for this CL, but looks like we have at least one more instance (cse_eop. […] Ack https://review.coreboot.org/c/coreboot/+/57684/comment/2f31cbd6_6f726632 PS6, Line 92: Note: The SRAM area is automatically cleared on G3 entry by the PMC > Is this note added to indicate that the crash log data would be empty when booting from G3? yes https://review.coreboot.org/c/coreboot/+/57684/comment/259b82f2_c883b17d PS6, Line 330: if (!is_dev_enabled(dev)) > Maybe like this ? […] Done https://review.coreboot.org/c/coreboot/+/57684/comment/5d248623_8c9378f7 PS6, Line 330: if (!is_dev_enabled(dev)) : return; > `init` shouldn't be called if device is disabled. So, this check is redundant. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc27bbdf35fcd680be224ba0a0e642c94d29bca3 Gerrit-Change-Number: 57684 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:48:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier, Andy Pont, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 12: (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61550/comment/d0f66990_4ad08c0a PS11, Line 88: CONFIG_TIANOCORE_TAG_OR_REV > shouldn't this be CONFIG_TIANOCORE_REPOSITORY instead? Yup, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Matt DeVillier (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Sean Rhodes, Martin Roth, Andy Pont, Stefan Reinauer. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 11: (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61550/comment/b2c818c9_78497d92 PS11, Line 88: CONFIG_TIANOCORE_TAG_OR_REV shouldn't this be CONFIG_TIANOCORE_REPOSITORY instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:45:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/nissa: Add devicetree
by Reka Norman (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kangheui Won, Krishna P Bhat D. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb: https://review.coreboot.org/c/coreboot/+/61141/comment/616cf7fd_74145c65 PS5, Line 34: " > You can always play it by ear and come back and refactor later once you have a better idea Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 6 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:32:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Subrata Banik, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Arthur Heymans, Andrey Petrov, Werner Zeh, Patrick Rudolph, EricR Lai, Tim Chu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/61518/comment/aa772123_b598c9c1 PS4, Line 1: config SOC_INTEL_COMMON_BLOCK_CSE : bool : default n : help : Driver for communication with Converged Security Engine (CSE) : over Host Embedded Controller Interface (HECI) : : config MAX_HECI_DEVICES : int : default 6 : : config DISABLE_HECI1_AT_PRE_BOOT : bool "Disable HECI1 at the end of boot" : depends on SOC_INTEL_COMMON_BLOCK_CSE : default n : help : This config decides the state of HECI1(CSE) device at the end of boot. : Mainboard users to select this config to make HECI1 `function disable` : prior to handing off to payload. : > @Tim, can you please take a look if this is what you asked me to align alphabetically. […] Perfect, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 21:32:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2022