coreboot-gerrit February 2022

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Change in coreboot[master]: soc/amd/common/psp_verstage: Add UART support to PSP console
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61610 ) Change subject: soc/amd/common/psp_verstage: Add UART support to PSP console ...................................................................... soc/amd/common/psp_verstage: Add UART support to PSP console This will allow PSP verstage to write logs to the serial console. We are no longer dependent on using a serial enabled PSP boot loader. Ideally we would delete this psp printk and use the standard printk. Since picasso doesn't currently support mapping the UART though, I'll keep it for now. BUG=b:215599230 TEST=Boot guybrush and verify PSP logs are output on serial console Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26 --- M src/soc/amd/common/psp_verstage/printk.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/61610/1 diff --git a/src/soc/amd/common/psp_verstage/printk.c b/src/soc/amd/common/psp_verstage/printk.c index c56f78c..526b8e7 100644 --- a/src/soc/amd/common/psp_verstage/printk.c +++ b/src/soc/amd/common/psp_verstage/printk.c @@ -4,11 +4,13 @@ #include <console/console.h> #include <console/cbmem_console.h> #include <console/streams.h> +#include <console/uart.h> #include <stdarg.h> void console_hw_init(void) { __cbmemc_init(); + __uart_init(); } int printk(int msg_level, const char *fmt, ...) @@ -33,8 +35,13 @@ return 0; cnt = vsnprintf(buf, sizeof(buf), fmt, args); - for (i = 0; i < cnt; i++) + for (i = 0; i < cnt; i++) { __cbmemc_tx_byte(buf[i]); + + if (buf[i] == '\n') + __uart_tx_byte('\r'); + __uart_tx_byte(buf[i]); + } svc_debug_print(buf); return i; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26 Gerrit-Change-Number: 61610 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina/psp_verstage: Implement get_uart_base
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61609 ) Change subject: soc/amd/sabrina/psp_verstage: Implement get_uart_base ...................................................................... soc/amd/sabrina/psp_verstage: Implement get_uart_base The Sabrina PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=None Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c --- M src/soc/amd/sabrina/psp_verstage/Makefile.inc A src/soc/amd/sabrina/psp_verstage/uart.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/61609/1 diff --git a/src/soc/amd/sabrina/psp_verstage/Makefile.inc b/src/soc/amd/sabrina/psp_verstage/Makefile.inc index 27539da..2338bf5 100644 --- a/src/soc/amd/sabrina/psp_verstage/Makefile.inc +++ b/src/soc/amd/sabrina/psp_verstage/Makefile.inc @@ -11,6 +11,7 @@ verstage-y += svc.c verstage-y += chipset.c +verstage-y += uart.c verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/sabrina/psp_verstage/uart.c b/src/soc/amd/sabrina/psp_verstage/uart.c new file mode 100644 index 0000000..1c89f10 --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/uart.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bl_uapp/bl_syscall_public.h> +#include <amdblocks/uart.h> +#include <types.h> + +uintptr_t get_uart_base(unsigned int idx) +{ + /* Mapping the UART is not supported. */ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c Gerrit-Change-Number: 61609 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/psp_verstage: Implement get_uart_base
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61608 ) Change subject: soc/amd/picasso/psp_verstage: Implement get_uart_base ...................................................................... soc/amd/picasso/psp_verstage: Implement get_uart_base The Picasso PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=Build and boot morphius Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6 --- M src/soc/amd/picasso/psp_verstage/Makefile.inc A src/soc/amd/picasso/psp_verstage/uart.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/61608/1 diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 41296c9..82d8efa 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -5,6 +5,7 @@ verstage-y += svc.c verstage-y += chipset.c +verstage-y += uart.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/psp_verstage/uart.c b/src/soc/amd/picasso/psp_verstage/uart.c new file mode 100644 index 0000000..1c89f10 --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/uart.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bl_uapp/bl_syscall_public.h> +#include <amdblocks/uart.h> +#include <types.h> + +uintptr_t get_uart_base(unsigned int idx) +{ + /* Mapping the UART is not supported. */ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6 Gerrit-Change-Number: 61608 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/psp_verstage: Implement get_uart_base
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61607 ) Change subject: soc/amd/cezanne/psp_verstage: Implement get_uart_base ...................................................................... soc/amd/cezanne/psp_verstage: Implement get_uart_base This will allow directly using the UART console. On PSP releases that don't support mapping the UART, we will just return NULL which is perfectly acceptable. BUG=b:215599230 TEST=Boot guybrush and verify verstage can print to the console Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic8d7f0fe00794a715756f92e3fb32c6b512cb8aa --- M src/soc/amd/cezanne/psp_verstage/Makefile.inc A src/soc/amd/cezanne/psp_verstage/uart.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/61607/1 diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc index ea9353d..547650d 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -9,6 +9,7 @@ verstage-y += svc.c verstage-y += chipset.c +verstage-y += uart.c verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/cezanne/psp_verstage/uart.c b/src/soc/amd/cezanne/psp_verstage/uart.c new file mode 100644 index 0000000..dff7c44 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/uart.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bl_uapp/bl_syscall_public.h> +#include <amdblocks/uart.h> +#include <types.h> + +static void *uart_bars[FCH_UART_ID_MAX - 1]; + +uintptr_t get_uart_base(unsigned int idx) +{ + uint32_t err; + + if (idx > ARRAY_SIZE(uart_bars)) + return 0; + + if (uart_bars[idx]) + return (uintptr_t)uart_bars[idx]; + + err = svc_map_fch_dev(FCH_IO_DEVICE_UART, idx, 0, &uart_bars[idx]); + if (err) { + svc_debug_print("Entering verstage on PSP\n"); + return 0; + } + + return (uintptr_t)uart_bars[idx]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d7f0fe00794a715756f92e3fb32c6b512cb8aa Gerrit-Change-Number: 61607 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/cezanne: Add support to map UARTs
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61606 ) Change subject: vc/amd/cezanne: Add support to map UARTs ...................................................................... vc/amd/cezanne: Add support to map UARTs This will allow coreboot to directly write to the UART controller. BUG=b:215599230 TEST=Try mapping the uart on guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 --- M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/61606/1 diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 4cf9e70..d88bfe1 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -88,10 +88,17 @@ FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, + FCH_IO_DEVICE_UART, FCH_IO_DEVICE_END, }; +enum fch_uart_id { + FCH_UART_ID_0 = 0, + FCH_UART_ID_1 = 1, + FCH_UART_ID_MAX, +}; + enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_0 = 0, FCH_I2C_CONTROLLER_ID_1 = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/61606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 Gerrit-Change-Number: 61606 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw p...
by Robert Zieba (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Rob Barnes, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61349 to look at the new patch set (#8). Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables ...................................................................... soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 --- M src/mainboard/google/zork/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/sabrina/Makefile.inc 5 files changed, 34 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61349/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Gerrit-Change-Number: 61349 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw p...
by Robert Zieba (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Rob Barnes, Karthik Ramasubramanian, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61349 ) Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Ported changes to Picasso and Sabrina per conversation with Felix. For Sabrina I enabled the VBOOT, VBOOT_SLOTS_RW_AB, VBOOT_STARTS_BEFORE_BOOTBLOCK Kconfigs for testing, as well as added temporary stub functions to get the verstage building so that the apu/amdfw_* would be built and I could verify that they ended up in the right places. -- To view, visit https://review.coreboot.org/c/coreboot/+/61349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Gerrit-Change-Number: 61349 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Feb 2022 23:12:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw p...
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61349 ) Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61349/comment/7e805eff_f62d9b80 PS7, Line 13: TEST Can you do a TIMELESS build as well and verify nothing changes? File src/soc/amd/cezanne/Makefile.inc: https://review.coreboot.org/c/coreboot/+/61349/comment/56e2a6b3_8b3bb746 PS7, Line 285: AMD_FW_AB_POSITION Why is this declared again? -- To view, visit https://review.coreboot.org/c/coreboot/+/61349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Gerrit-Change-Number: 61349 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Feb 2022 23:11:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw p...
by Robert Zieba (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61349 to look at the new patch set (#7). Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables ...................................................................... soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 --- M src/mainboard/google/zork/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/sabrina/Makefile.inc 5 files changed, 38 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61349/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Gerrit-Change-Number: 61349 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/nivviks: Initialise overridetree
by Reka Norman (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kangheui Won, Rizwan Qureshi, Tim Wawrzynczak, Krishna P Bhat D, Usha P. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61605 ) Change subject: mb/google/brya/var/nivviks: Initialise overridetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/nivviks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/61605/comment/a585717f_f134aff1 PS1, Line 10: SaGv_Enabled Not sure if this should be disabled for initial bringup. -- To view, visit https://review.coreboot.org/c/coreboot/+/61605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Gerrit-Change-Number: 61605 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 23:00:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2022