coreboot-gerrit February 2022

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Change in coreboot[master]: mb/asus/p2b: list all unused Super I/O resources
by Keith Hui (Code Review) 03 Feb '22

03 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41459 ) Change subject: mb/asus/p2b: list all unused Super I/O resources ...................................................................... mb/asus/p2b: list all unused Super I/O resources Some Super I/O resources were unused and not listed, causing warnings during resource allocation. Suppress these warnings by setting them to zero. Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41459/1 diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 9f7f63e..7ee69e4 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -18,6 +18,7 @@ device pnp 3f0.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 0 end device pnp 3f0.2 on # COM1 io 0x60 = 0x3f8 @@ -34,6 +35,9 @@ irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 3f0.7 on # GPIO 1 + io 0x60 = 0 + io 0x62 = 0 + irq 0x70 = 0 end device pnp 3f0.8 on # GPIO 2 end -- To view, visit https://review.coreboot.org/c/coreboot/+/41459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Gerrit-Change-Number: 41459 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/nivviks: Initialise overridetree
by Reka Norman (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Tim Wawrzynczak. Hello Reka Norman, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61605 to look at the new patch set (#2). Change subject: mb/google/brya/var/nivviks: Initialise overridetree ...................................................................... mb/google/brya/var/nivviks: Initialise overridetree Add an initial overridetree for nivviks based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/nivviks/overridetree.cb 2 files changed, 324 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/61605/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Gerrit-Change-Number: 61605 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/nivviks: Initialise overridetree
by Reka Norman (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Reka Norman. Hello Reka Norman, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/61605 to review the following change. Change subject: mb/google/brya/var/nivviks: Initialise overridetree ...................................................................... mb/google/brya/var/nivviks: Initialise overridetree Add an initial overridetree for nivviks based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/nivviks/overridetree.cb 2 files changed, 324 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/61605/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 0a3b1d9..83c148f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -80,6 +80,7 @@ config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_INTEL_MIPI_CAMERA config BOARD_GOOGLE_NEREID bool "-> Nereid" diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index ee86142..ec52b73 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -1,4 +1,325 @@ +fw_config + field DB_USB 0 1 + option DB_NONE 0 + option DB_1C_1A 1 + option DB_1C_LTE 2 + end +end + chip soc/intel/alderlake - device domain 0 on - end + register "SaGv" = "SaGv_Enabled" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + device domain 0 on + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe DB_USB DB_1C_LTE + end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/61605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Gerrit-Change-Number: 61605 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Introduce SCMI Kconfig options
by Keith Hui (Code Review) 03 Feb '22

03 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48921 ) Change subject: sb/intel: Introduce SCMI Kconfig options ...................................................................... sb/intel: Introduce SCMI Kconfig options Introduce two options for enabling SMBus Control Method Interface [1] support. 1. HAVE_SCMI is to be set by southbridges that implements SCMI in the DSDT. That implementation should be conditional on USE_SCMI. See below. 2. USE_SCMI is guarded by HAVE_SCMI and actually provides the option to the user in Kconfig. Enabling it adds the SCMI implementation to the DSDT and make it usable. Boards that require this support for board function should set it in their BOARD_SPECIFIC_OPTIONS, which will lock this option on. It will be used by CB:41735 but are designed for wider adoption e.g. by CB:44507 [1] http://smbus.org/specs/smbus_cmi10.pdf [41735] https://review.coreboot.org/c/coreboot/+/41735 [44507] https://review.coreboot.org/c/coreboot/+/44507 Change-Id: Ib1e176b6495fa673fd46cbb8f8fd7c5a41ababde Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/common/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48921/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25..11ba094 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -105,3 +105,22 @@ hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS default 0x400 + +config HAVE_SCMI + bool + help + Selected by southbridges that implements SCMI in their DSDT. + See http://smbus.org/specs/smbus_cmi10.pdf for details. + +config USE_SCMI + bool "Enable SMBus Control Method Interface (SCMI)" + depends on HAVE_SCMI && HAVE_ACPI_TABLES + help + Adds extra access methods conforming to the SMBus Control Method Interface (SCMI) + specification to the SMBus ACPI device. This provides alternate SMBus access if + regular means are unavailable due to e.g. resource conflicts. + + ASUS P3B-F mainboard is known to need this. + + If you say Y here, you will have to blacklist the native driver and instead use + i2c-scmi driver to access SMBus-connected devices. -- To view, visit https://review.coreboot.org/c/coreboot/+/48921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e176b6495fa673fd46cbb8f8fd7c5a41ababde Gerrit-Change-Number: 48921 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cyan: Fixup variant GPIOs
by Matt DeVillier (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Tim Wawrzynczak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61585 ) Change subject: mb/google/cyan: Fixup variant GPIOs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I found a few of the schematics, I couldn't find all. […] Relm has been tested, Wizpig has not, but AFAICT the audio config is exactly the same for all variants outside of cyan, as they're based on the strago baseboard. The JD and codec interrupts are also set identically in onboard.h for those. -- To view, visit https://review.coreboot.org/c/coreboot/+/61585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Gerrit-Change-Number: 61585 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: CoolStar Organization <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 22:32:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Hoglin: Switch to using i2c TPM
by Shelley Chen (Code Review) 03 Feb '22

03 Feb '22

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61604 ) Change subject: Hoglin: Switch to using i2c TPM ...................................................................... Hoglin: Switch to using i2c TPM Redefine Hoglin to be used for Qualcomm's CRD 3.0 board, which uses i2c for TPM instead of SPI. From now on, the Piglin board will be used for all the Qualcomm reference boards that use SPI for TPM. BUG=b:206581077 BRANCH=None TEST=hacked an 8MB image and make sure boots on herobrine board Change-Id: Ie1d71ec8b01f305c1c8fa815a0fb9b7ee022cc19 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/61604/1 diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 511e4cb..c6dfaab 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -24,8 +24,8 @@ select SPI_FLASH_WINBOND select SPI_FLASH_MACRONIX select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN - select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_HEROBRINE_REV0 || BOARD_GOOGLE_HEROBRINE + select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_GOOGLE_PIGLIN + select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_HEROBRINE_REV0 || BOARD_GOOGLE_HEROBRINE || BOARD_GOOGLE_HOGLIN select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_SENOR config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/61604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1d71ec8b01f305c1c8fa815a0fb9b7ee022cc19 Gerrit-Change-Number: 61604 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Define enum cpu_perf_eff_type type for core types
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61459 ) Change subject: soc/intel/common: Define enum cpu_perf_eff_type type for core types ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Gerrit-Change-Number: 61459 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 22:19:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Fixup variant GPIOs
by Tim Wawrzynczak (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Matt DeVillier. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61585 ) Change subject: mb/google/cyan: Fixup variant GPIOs ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: I found a few of the schematics, I couldn't find all. e.g. Wizpig & Relm, I do see some of those you set to NC that are supposedly connected to the headphone jack detect signal on the schematic, but on the other hand there is also a note saying it was removed at one point for relm, but not wizpig.... /shrugs If this works for you, it seems OK. I'll give +1 for now, and +2 later if no one else has any objections. -- To view, visit https://review.coreboot.org/c/coreboot/+/61585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Gerrit-Change-Number: 61585 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: CoolStar Organization <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 22:18:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 12: (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61550/comment/5acb5635_f78b13ff PS12, Line 89: rm -rf $(project_dir) > This seems a little dangerous to me. […] That's a very good idea - set project_dir to: $(word 4,$(subst /, ,$(CONFIG_TIANOCORE_REPOSITORY)))+$(word 2,$(subst /, ,$(CONFIG_TIANOCORE_TAG_OR_REV))) i.e. mrchromebox+uefipayload_202202 -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 22:08:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Martin Roth (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Sean Rhodes, Matt DeVillier, Andy Pont, Stefan Reinauer. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Patch Set 12: Code-Review+2 (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/61550/comment/1a0a02bb_a9bb1af0 PS12, Line 89: rm -rf $(project_dir) This seems a little dangerous to me. Maybe just bail out with an error here telling them to delete the directory and rebuild if they want to switch repos? Alternatively, switch the directory name to correspond with which repo is being used so that it would just switch directories and download the other repo? I know that some people actually develop in their payloads directories, and I don't want people to lose their data because of a slip up. That could happen in a follow-on patch if you want. -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 22:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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