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Change in coreboot[master]: mb/google/skyrim: Add new mainboard
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61565 ) Change subject: mb/google/skyrim: Add new mainboard ...................................................................... mb/google/skyrim: Add new mainboard Skyrim is a new Google mainboard with AMD Sabrina SOC. BUG=b:214413553 TEST=util/abuild/abuild -t GOOGLE_SKYRIM --clean Change-Id: I008fea4aa163b8aa66e86735b29b3fdc4e08a327 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61565 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> --- A src/mainboard/google/skyrim/Kconfig A src/mainboard/google/skyrim/Kconfig.name A src/mainboard/google/skyrim/Makefile.inc A src/mainboard/google/skyrim/board_info.txt A src/mainboard/google/skyrim/bootblock.c A src/mainboard/google/skyrim/chromeos.fmd A src/mainboard/google/skyrim/dsdt.asl A src/mainboard/google/skyrim/mainboard.c A src/mainboard/google/skyrim/port_descriptors.c A src/mainboard/google/skyrim/variants/baseboard/devicetree.cb A src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h A src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 12 files changed, 162 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig new file mode 100644 index 0000000..619ac64 --- /dev/null +++ b/src/mainboard/google/skyrim/Kconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_SKYRIM + def_bool n + +if BOARD_GOOGLE_BASEBOARD_SKYRIM + +config AMD_FWM_POSITION_INDEX + int + default 3 + help + TODO: might need to be adapted for better placement of files in cbfs + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_AMD_SABRINA + +config DEVICETREE + default "variants/baseboard/devicetree.cb" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + +config MAINBOARD_DIR + default "google/skyrim" + +config MAINBOARD_FAMILY + string + default "Google_Skyrim" + +config MAINBOARD_PART_NUMBER + default "Skyrim" if BOARD_GOOGLE_SKYRIM + +endif # BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name new file mode 100644 index 0000000..a36235c --- /dev/null +++ b/src/mainboard/google/skyrim/Kconfig.name @@ -0,0 +1,5 @@ +comment "Skyrim" + +config BOARD_GOOGLE_SKYRIM + bool "-> Skyrim" + select BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc new file mode 100644 index 0000000..df2762d --- /dev/null +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += port_descriptors.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/skyrim/board_info.txt b/src/mainboard/google/skyrim/board_info.txt new file mode 100644 index 0000000..9588901 --- /dev/null +++ b/src/mainboard/google/skyrim/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Skyrim +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c new file mode 100644 index 0000000..dd4c151 --- /dev/null +++ b/src/mainboard/google/skyrim/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <baseboard/variants.h> + +void bootblock_mainboard_early_init(void) +{ + /* TODO: Perform mainboard initialization */ +} diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd new file mode 100644 index 0000000..a6dbc2c --- /dev/null +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -0,0 +1,34 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + RW_MRC_CACHE(PRESERVE) 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/skyrim/dsdt.asl b/src/mainboard/google/skyrim/dsdt.asl new file mode 100644 index 0000000..80a9c1f --- /dev/null +++ b/src/mainboard/google/skyrim/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include <acpi/dsdt_top.asl> + #include <soc.asl> +} diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c new file mode 100644 index 0000000..3dc2c41 --- /dev/null +++ b/src/mainboard/google/skyrim/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + /* TODO: Perform mainboard initialization */ +} + +static void mainboard_enable(struct device *dev) +{ + /* TODO: Enable mainboard */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c new file mode 100644 index 0000000..56bd9f3 --- /dev/null +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + /* TODO: Initialize DXIO and DDI descriptors */ +} diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..ed77b0b --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/sabrina + device domain 0 on + end # domain +end # chip soc/amd/sabrina diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h new file mode 100644 index 0000000..b94afac --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..927af2f --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008fea4aa163b8aa66e86735b29b3fdc4e08a327 Gerrit-Change-Number: 61565 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/chausie/devicetree: update I2C RX levels to match board design
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61569 ) Change subject: mb/amd/chausie/devicetree: update I2C RX levels to match board design ...................................................................... mb/amd/chausie/devicetree: update I2C RX levels to match board design Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/chausie/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 6067b18..8cc23e1 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -14,10 +14,10 @@ }" # I2C Pad Control RX Select Configuration - register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" - register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" - register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" - register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" register "s0ix_enable" = "true" 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Gerrit-Change-Number: 61569 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/i2c: factor out common I2C pad configuration
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61568 ) Change subject: soc/amd/*/i2c: factor out common I2C pad configuration ...................................................................... soc/amd/*/i2c: factor out common I2C pad configuration The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/amd/majolica/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/i2c.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/common/block/i2c/Kconfig M src/soc/amd/common/block/i2c/Makefile.inc A src/soc/amd/common/block/i2c/i2c_pad_ctrl.c A src/soc/amd/common/block/i2c/i2c_pad_def.h M src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/chip.h M src/soc/amd/sabrina/i2c.c M src/soc/amd/sabrina/include/soc/southbridge.h 19 files changed, 134 insertions(+), 145 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 19815b3..6067b18 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -14,10 +14,10 @@ }" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" register "s0ix_enable" = "true" diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 7bb0db1..9758e9c 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -14,10 +14,10 @@ }" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" register "s0ix_enable" = "true" diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index ac2856e..104ba79 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -75,10 +75,10 @@ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Trackpad - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Touchscreen - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" # Trackpad + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" # Touchscreen + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" # Audio/SAR + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 620c650..f0b7c27 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index d007a84..1e59153 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -4,6 +4,7 @@ #define CEZANNE_CHIP_H #include <amdblocks/chip.h> +#include <amdblocks/i2c.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -15,7 +16,7 @@ struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; - u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; /* Enable S0iX support */ bool s0ix_enable; diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index 1fcab6a..bf47b81 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> #include <amdblocks/i2c.h> #include <console/console.h> #include <soc/i2c.h> @@ -36,24 +35,11 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_cezanne_config *config = config_of_soc(); - uint32_t pad_ctrl; - if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel)) + if (bus >= ARRAY_SIZE(config->i2c_pad)) return; - pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus]; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? - I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 9c68d38..4e44b89 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -112,33 +112,6 @@ #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ #define BP_X48M0_S0I3_DIS BIT(4) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define MISC_I2C0_PAD_CTRL 0xd8 -#define MISC_I2C1_PAD_CTRL 0xdc -#define MISC_I2C2_PAD_CTRL 0xe0 -#define MISC_I2C3_PAD_CTRL 0xe4 -#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) -#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -#define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) -#define I2C_PAD_CTRL_RX_SHIFT 4 -#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) -#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 -#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) -#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) -#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ -#define I2C_PAD_CTRL_CAP_DOWN BIT(12) -#define I2C_PAD_CTRL_CAP_UP BIT(13) -#define I2C_PAD_CTRL_RES_DOWN BIT(14) -#define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) -#define I2C_PAD_CTRL_SPARE0 BIT(17) -#define I2C_PAD_CTRL_SPARE1 BIT(18) void fch_pre_init(void); void fch_early_init(void); diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig index 5d8498c..7c1ea0e 100644 --- a/src/soc/amd/common/block/i2c/Kconfig +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -2,3 +2,9 @@ bool help Select this option to add FCH I2C controller functions to the build. + +config SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + bool + help + Select this option to add FCH I2C pad configuration functions to the + build. diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc index 8af7796..3d2cdf6 100644 --- a/src/soc/amd/common/block/i2c/Makefile.inc +++ b/src/soc/amd/common/block/i2c/Makefile.inc @@ -1 +1,2 @@ all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c diff --git a/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c new file mode 100644 index 0000000..cdb7900 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> +#include <console/console.h> +#include <types.h> +#include "i2c_pad_def.h" + +void fch_i2c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl) +{ + uint32_t pad_ctrl; + + pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); + + pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; + pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; + + switch (ctrl->rx_level) { + case I2C_PAD_RX_NO_CHANGE: + break; + case I2C_PAD_RX_OFF: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_OFF; + break; + case I2C_PAD_RX_3_3V: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; + break; + case I2C_PAD_RX_1_8V: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_1_8V; + break; + default: + printk(BIOS_WARNING, "Invalid I2C pad RX level for bus %u\n", bus); + break; + } + + pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; + pad_ctrl |= speed == I2C_SPEED_STANDARD ? + I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; + pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; + misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); +} diff --git a/src/soc/amd/common/block/i2c/i2c_pad_def.h b/src/soc/amd/common/block/i2c/i2c_pad_def.h new file mode 100644 index 0000000..76e10cd --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c_pad_def.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_I2C_PAD_DEF_H +#define AMD_BLOCK_I2C_PAD_DEF_H + +#include <types.h> + +#define MISC_I2C0_PAD_CTRL 0xd8 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) + +#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define I2C_PAD_CTRL_NG_NORMAL 0xc +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) +#define I2C_PAD_CTRL_RX_SHIFT 4 +#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 +#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) +#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) +#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ +#define I2C_PAD_CTRL_CAP_DOWN BIT(12) +#define I2C_PAD_CTRL_CAP_UP BIT(13) +#define I2C_PAD_CTRL_RES_DOWN BIT(14) +#define I2C_PAD_CTRL_RES_UP BIT(15) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_SPARE0 BIT(17) +#define I2C_PAD_CTRL_SPARE1 BIT(18) +/* The following bits are reserved in Picasso and Cezanne */ +#define I2C_PAD_CTRL_PD_EN BIT(19) +#define I2C_PAD_CTRL_COMP_SEL BIT(20) +#define I2C_PAD_CTRL_RES_BIAS_EN BIT(21) + +#endif /* AMD_BLOCK_I2C_PAD_DEF_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index 6660e37..54651a9 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -56,6 +56,21 @@ size_t num_pins; }; +enum i2c_pad_rx_level { + I2C_PAD_RX_NO_CHANGE, + I2C_PAD_RX_OFF, + I2C_PAD_RX_3_3V, + I2C_PAD_RX_1_8V, +}; + +struct i2c_pad_control { + enum i2c_pad_rx_level rx_level; +}; + +void fch_i2c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl); + /* Helper function to perform misc I2C configuration specific to SoC. */ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4567d55..ebcbd62 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 40cf556..ebc833d 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -40,22 +40,13 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { - uint32_t pad_ctrl; + /* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this + configurable. */ + const struct i2c_pad_control ctrl = { + .rx_level = I2C_PAD_RX_3_3V, + }; - pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? - I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); + fch_i2c_pad_init(bus, cfg->speed, &ctrl); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 2a3e38b..b8dd67b 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -92,33 +92,6 @@ #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define MISC_CLK_CNTL1 0x40 #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define MISC_I2C0_PAD_CTRL 0xd8 -#define MISC_I2C1_PAD_CTRL 0xdc -#define MISC_I2C2_PAD_CTRL 0xe0 -#define MISC_I2C3_PAD_CTRL 0xe4 -#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) -#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -#define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) -#define I2C_PAD_CTRL_RX_SHIFT 4 -#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) -#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 -#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) -#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) -#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ -#define I2C_PAD_CTRL_CAP_DOWN BIT(12) -#define I2C_PAD_CTRL_CAP_UP BIT(13) -#define I2C_PAD_CTRL_RES_DOWN BIT(14) -#define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) -#define I2C_PAD_CTRL_SPARE0 BIT(17) -#define I2C_PAD_CTRL_SPARE1 BIT(18) #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index ca7a83c..2e34e3f 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -52,6 +52,7 @@ select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h index a7acb7f..c272f9f 100644 --- a/src/soc/amd/sabrina/chip.h +++ b/src/soc/amd/sabrina/chip.h @@ -6,6 +6,7 @@ #define SABRINA_CHIP_H #include <amdblocks/chip.h> +#include <amdblocks/i2c.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -17,7 +18,7 @@ struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; - u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; /* Enable S0iX support */ bool s0ix_enable; diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c index 89751d5..88da74e 100644 --- a/src/soc/amd/sabrina/i2c.c +++ b/src/soc/amd/sabrina/i2c.c @@ -2,7 +2,6 @@ /* TODO: Check if this is still correct */ -#include <amdblocks/acpimmio.h> #include <amdblocks/i2c.h> #include <console/console.h> #include <soc/i2c.h> @@ -38,24 +37,11 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_sabrina_config *config = config_of_soc(); - uint32_t pad_ctrl; - if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel)) + if (bus >= ARRAY_SIZE(config->i2c_pad)) return; - pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus]; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? - I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index e85a052..e755d50 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -113,36 +113,6 @@ #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ #define BP_X48M0_S0I3_DIS BIT(4) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define MISC_I2C0_PAD_CTRL 0xd8 -#define MISC_I2C1_PAD_CTRL 0xdc -#define MISC_I2C2_PAD_CTRL 0xe0 -#define MISC_I2C3_PAD_CTRL 0xe4 -#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) -#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -#define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) -#define I2C_PAD_CTRL_RX_SHIFT 4 -#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) -#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 -#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) -#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) -#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ -#define I2C_PAD_CTRL_CAP_DOWN BIT(12) -#define I2C_PAD_CTRL_CAP_UP BIT(13) -#define I2C_PAD_CTRL_RES_DOWN BIT(14) -#define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) -#define I2C_PAD_CTRL_SPARE0 BIT(17) -#define I2C_PAD_CTRL_SPARE1 BIT(18) -#define I2C_PAD_CTRL_PD_EN BIT(19) -#define I2C_PAD_CTRL_COMP_SEL BIT(20) -#define I2C_PAD_CTRL_RES_BIAS_EN BIT(21) void fch_pre_init(void); void fch_early_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/61568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Gerrit-Change-Number: 61568 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: security/vboot/secdata_tpm: Set up space for widevine counter info
by Karthik Ramasubramanian (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Andrey Pronin, Raul Rangel, Mohan Viswanathan, Name of user not set #1004133, Jon Murphy, Paul Menzel, Julius Werner, Rob Barnes, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61521 ) Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > The additional non-volatile space is required to store the status of the counters in use. […] Julius, Based on offline conversation I had, as part of protected playback session widevine application creates a counter. Widevine application deletes the counter at the end of the session. These timer creation and deletion operations are tracked as counter status. I am not sure if there is a counter reset operation. I did not see any such command in TCG_TPM2_r1p59_Part3_Commands_code_pub. Mohan/Nimesh, Can you also please share the layout of the space? -- To view, visit https://review.coreboot.org/c/coreboot/+/61521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80de9024195452a235cbed73e21410f848c91722 Gerrit-Change-Number: 61521 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mohan Viswanathan Gerrit-CC: Name of user not set #1004133 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mohan Viswanathan Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 23:45:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mohan Viswanathan Comment-In-Reply-To: Name of user not set #1004133 Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61567 ) Change subject: soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro ...................................................................... soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/i2c.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/sabrina/i2c.c M src/soc/amd/sabrina/include/soc/southbridge.h 6 files changed, 9 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index 153fa7c..1fcab6a 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -37,13 +37,11 @@ { const struct soc_amd_cezanne_config *config = config_of_soc(); uint32_t pad_ctrl; - int misc_reg; if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel)) return; - misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; - pad_ctrl = misc_read32(misc_reg); + pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; @@ -55,7 +53,7 @@ pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - misc_write32(misc_reg, pad_ctrl); + misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 113395e..9c68d38 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -116,6 +116,7 @@ #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 #define MISC_I2C3_PAD_CTRL 0xe4 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) #define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define I2C_PAD_CTRL_NG_NORMAL 0xc #define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 925a832..40cf556 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -41,10 +41,8 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { uint32_t pad_ctrl; - int misc_reg; - misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; - pad_ctrl = misc_read32(misc_reg); + pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; @@ -57,7 +55,7 @@ I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - misc_write32(misc_reg, pad_ctrl); + misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index d439e92..2a3e38b 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -96,6 +96,7 @@ #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 #define MISC_I2C3_PAD_CTRL 0xe4 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) #define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define I2C_PAD_CTRL_NG_NORMAL 0xc #define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c index f3eaf4e..89751d5 100644 --- a/src/soc/amd/sabrina/i2c.c +++ b/src/soc/amd/sabrina/i2c.c @@ -39,13 +39,11 @@ { const struct soc_amd_sabrina_config *config = config_of_soc(); uint32_t pad_ctrl; - int misc_reg; if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel)) return; - misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; - pad_ctrl = misc_read32(misc_reg); + pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; @@ -57,7 +55,7 @@ pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - misc_write32(misc_reg, pad_ctrl); + misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index 7b5644b..e85a052 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -117,6 +117,7 @@ #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 #define MISC_I2C3_PAD_CTRL 0xe4 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) #define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define I2C_PAD_CTRL_NG_NORMAL 0xc #define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b Gerrit-Change-Number: 61567 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/i2c: drop unused mainboard_i2c_override
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61566 ) Change subject: soc/amd/*/i2c: drop unused mainboard_i2c_override ...................................................................... soc/amd/*/i2c: drop unused mainboard_i2c_override No mainboard in the current tree implements mainboard_i2c_override. In a follow-up commit the i2c_pad_control struct is introduced to be able to make more parameters controllable by devicetree settings in the future. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/i2c.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/sabrina/i2c.c M src/soc/amd/sabrina/include/soc/southbridge.h 6 files changed, 0 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index 008b261..153fa7c 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -33,8 +33,6 @@ } #endif -__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } - void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_cezanne_config *config = config_of_soc(); @@ -57,8 +55,6 @@ pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - mainboard_i2c_override(bus, &pad_ctrl); misc_write32(misc_reg, pad_ctrl); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 4f372ad..113395e 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -147,7 +147,4 @@ void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); -/* Allow the board to change the default I2C pad configuration */ -void mainboard_i2c_override(int bus, uint32_t *pad_settings); - #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 18660f6..925a832 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -38,8 +38,6 @@ } #endif -__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } - void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { uint32_t pad_ctrl; @@ -59,7 +57,6 @@ I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - mainboard_i2c_override(bus, &pad_ctrl); misc_write32(misc_reg, pad_ctrl); } diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 2936600..d439e92 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -136,7 +136,4 @@ void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); -/* Allow the board to change the default I2C pad configuration */ -void mainboard_i2c_override(int bus, uint32_t *pad_settings); - #endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c index 2030f40..f3eaf4e 100644 --- a/src/soc/amd/sabrina/i2c.c +++ b/src/soc/amd/sabrina/i2c.c @@ -35,8 +35,6 @@ } #endif -__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } - void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_sabrina_config *config = config_of_soc(); @@ -59,8 +57,6 @@ pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - mainboard_i2c_override(bus, &pad_ctrl); misc_write32(misc_reg, pad_ctrl); } diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index 4b25c5e..7b5644b 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -151,7 +151,4 @@ void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); -/* Allow the board to change the default I2C pad configuration */ -void mainboard_i2c_override(int bus, uint32_t *pad_settings); - #endif /* AMD_SABRINA_SOUTHBRIDGE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03 Gerrit-Change-Number: 61566 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/lapic: Fix choice X2APIC_ONLY
by Angel Pons (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Nico Huber, Wonkyu Kim, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60213 ) Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Gerrit-Change-Number: 60213 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 23:39:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers: spi_flash: Addressing mode change for SPI NOR
by Julius Werner (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Shelley Chen, Ravi kumar, Sudheer Amrabadi, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: drivers: spi_flash: Addressing mode change for SPI NOR ...................................................................... Patch Set 111: (4 comments) File src/drivers/spi/Kconfig: https://review.coreboot.org/c/coreboot/+/50586/comment/c5075ecf_9b52fca6 PS111, Line 164: config SPI_FLASH_WINBOND_MODE3 Please remove your previous code that is no longer used. https://review.coreboot.org/c/coreboot/+/50586/comment/4c147ffb_c9f7393c PS111, Line 181: Exit 4 byte addressing mode for SPI nor. "This will send an Exit 4-Byte Address Mode (E9h) command before the first access to the SPI flash. On some platforms with SPI flashes larger than 32MB, the SPI flash may power up in 4-byte addressing mode and this command needs to be sent before coreboot's 3-byte address commands can be interpreted correctly. On flashes that don't support 4-byte addressing mode or where it is already disabled, this command should be a no-op." File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/50586/comment/b0821cab_1036d2a2 PS111, Line 15: #define CMD_EXIT_4BYTE_ADDR_MODE 0xe9 Please define this in spi_flash_internal.h with the rest of the commands. https://review.coreboot.org/c/coreboot/+/50586/comment/e6bc62e0_b0e30a7f PS111, Line 521: #if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && ENV_INITIAL_STAGE) This can be if(), not #if -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 111 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 23:22:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UART
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61612 ) Change subject: mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UART ...................................................................... mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UART This will make debugging boot failures with a non-serial firmware easier. If we encounter an error that requires a reboot, this will dump the entire CBMEM contents onto the UART. This is especially helpful during S0i3 resume because the PSP verstage console logs are not exposed anywhere. BUG=b:215599230 TEST=Cause verstage error in S0i3 with non-serial firmware and see that the verstage logs were dumped to the UART before rebooting. Entering PSP verstage S0i3 resume tpm_setup failed rv:1 VB2:vb2api_fail() Need recovery, reason: 0x3f / 0xcc Saving nvdata Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I908037527206cc7bed2302fab60b2912d6dabc73 --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/61612/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 43cbdde..b2fce84 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -12,6 +12,7 @@ def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select CONSOLE_CBMEM_DUMP_TO_UART if !CONSOLE_SERIAL select DISABLE_KEYBOARD_RESET_PIN select DISABLE_SPI_FLASH_ROM_SHARING select DRIVERS_ACPI_THERMAL_ZONE -- To view, visit https://review.coreboot.org/c/coreboot/+/61612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I908037527206cc7bed2302fab60b2912d6dabc73 Gerrit-Change-Number: 61612 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61611 ) Change subject: soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS ...................................................................... soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS Now that PSP verstage can directly write to the UART, we no longer need to manually dump the cbmem contents. Ideally if we can get picasso to add support for mapping the UART, or if we implement bit banging we can delete this functionality completely. BUG=b:215599230 TEST=Boot guybrush and verify verstage logs aren't printed twice Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id70b24625c3b2f3d6fe470cf227a0083f5b974f9 --- M src/soc/amd/cezanne/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/61611/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 620c650..d26192a 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -16,7 +16,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI -- To view, visit https://review.coreboot.org/c/coreboot/+/61611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id70b24625c3b2f3d6fe470cf227a0083f5b974f9 Gerrit-Change-Number: 61611 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2022