Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61266 )

Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
......................................................................

mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1

Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.

BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled

Signed-off-by: Meera Ravindranath <[e-mail]>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266
Tested-by: build bot (Jenkins) <[e-mail]>
Reviewed-by: Tim Wawrzynczak <[e-mail]>
Reviewed-by: Sridhar Siricilla <[e-mail]>
Reviewed-by: Nick Vaccaro <[e-mail]>
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved
  Sridhar Siricilla: Looks good to me, but someone else must approve



diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 23071fe..408d380 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -38,6 +38,7 @@
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
 	register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -121,6 +122,7 @@
 				device generic 0 on end
 			end
 		end
+		device ref pcie_rp6 off end
 		device ref pcie_rp8 on
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Gerrit-Change-Number: 61266
Gerrit-PatchSet: 4
Gerrit-Owner: Meera Ravindranath <[e-mail]>
Gerrit-Reviewer: Felix Held <[e-mail]>
Gerrit-Reviewer: Mark Hsieh <[e-mail]>
Gerrit-Reviewer: Maulik V Vaghela <[e-mail]>
Gerrit-Reviewer: Nick Vaccaro <[e-mail]>
Gerrit-Reviewer: Sridhar Siricilla <[e-mail]>
Gerrit-Reviewer: Tim Wawrzynczak <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Anfernee Chen <[e-mail]>
Gerrit-CC: Casper Chang <[e-mail]>
Gerrit-CC: Kane Chen <[e-mail]>
Gerrit-CC: Malik Hsu <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-CC: Scott Chao <[e-mail]>
Gerrit-MessageType: merged