Felix Held submitted this change.
mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.
BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 23071fe..408d380 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -38,6 +38,7 @@
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+ register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -121,6 +122,7 @@
device generic 0 on end
end
end
+ device ref pcie_rp6 off end
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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