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Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base
......................................................................
soc/intel/graphics: Create Kconfig for shifting graphic memory base
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to shift graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in KConfig under soc folder.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/14
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Name of user not set #1004133 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61445 )
Change subject: mb/google/guybrush: Add the fw SPL to amdfw.cfg
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg:
https://review.coreboot.org/c/coreboot/+/61445/comment/7cc1cd04_5442db8a
PS1, Line 27: TypeId0x55_SplTable_Prod_CZN_Chrome
> Has this been pushed upstream yet? Who generated the binary, why is the chromeos specific?
Not sure this is required upstream. This is required for ChromeOs to rollback Widevine Trusted Application/ any other PSP firmware binary that has any vulnerabilities identified.
Please refer to https://partnerissuetracker.corp.google.com/issues/175935540#comment30 for the test results. Also check the bug for an overview of the feature
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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 10:
(2 comments)
File src/drivers/wifi/generic/acpi.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139880):
https://review.coreboot.org/c/coreboot/+/61020/comment/a1e07cf9_b2b0bf7d
PS10, Line 489: union wifi_sar_limits sar_limits = {{NULL, NULL, NULL, NULL, NULL}};
space required after that close brace '}'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139880):
https://review.coreboot.org/c/coreboot/+/61020/comment/e0fec7c0_69fcd2a1
PS10, Line 511: if (sar_limits.dsm != NULL) {
braces {} are not necessary for single statement blocks
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Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61020
to look at the new patch set (#11).
Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
src/driver/wifi: Add _DSM method for DDRRFIM
coreboot need to propagate the CnviDdrRfim value info of the feature
enable/disable state into the CNVi via the WiFi DSM ACPI object. This
patch adds _DSM method for that.
Add support for following 2 function in _DSM method
- Function 0: Function Support Query Returns a bitmask of functions
supported.
- Function 3: RFI enablement 0 Feature Enable 1 Feature Disable
BUG=b:201724512
TEST=Build, boot brya0 and dump SSDT entries
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x09
})
}
If ((Local1 == One)){}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03))
{
Return (Zero)
}
Return (Buffer (One)
{
0x00
})
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37
---
M src/drivers/wifi/generic/acpi.c
1 file changed, 62 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61020/11
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Sudheer Amrabadi has uploaded a new patch set (#111) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50586 )
Change subject: drivers: spi_flash: Addressing mode change for SPI NOR
......................................................................
drivers: spi_flash: Addressing mode change for SPI NOR
As 4-byte addressing mode is not support in coreboot, change the
addressing mode of SPI nor from 4-bytes to 3-bytes.
BUG=b:215605946
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan(a)quicinc.com>
Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu(a)quicinc.com>
Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4
---
M src/drivers/spi/Kconfig
M src/drivers/spi/spi_flash.c
2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50586/111
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Sudheer Amrabadi has uploaded a new patch set (#13) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59611 )
Change subject: qualcomm/sc7280: Add display external clock support in coreboot
......................................................................
qualcomm/sc7280: Add display external clock support in coreboot
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.
BUG=b:182963902,216687885
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
---
M src/soc/qualcomm/sc7280/clock.c
M src/soc/qualcomm/sc7280/include/soc/clock.h
2 files changed, 53 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59611/13
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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 10:
This change is ready for review.
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