coreboot-gerrit February 2022

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCIe RPs
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61415 ) Change subject: mb/siemens/mc_ehl2: Disable PCIe RPs ...................................................................... mb/siemens/mc_ehl2: Disable PCIe RPs With latest hardware revision only PCIe RP2 and RP7 are used on this mainboard. Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61415 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 4 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4982384..438419a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -43,18 +43,15 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" @@ -64,17 +61,11 @@ register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports - register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports - register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" - register "PcieRpLtrDisable[2]" = "true" - register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true" # Storage (SDCARD/EMMC) related UPDs @@ -156,10 +147,7 @@ device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.2 on end # RP3 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) -- To view, visit https://review.coreboot.org/c/coreboot/+/61415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da Gerrit-Change-Number: 61415 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable SATA
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61414 ) Change subject: mb/siemens/mc_ehl2: Disable SATA ...................................................................... mb/siemens/mc_ehl2: Disable SATA With latest hardware revision SATA interface is no longer used on this mainboard. The mainboard is still in development and not yet released and for this reason there may still be adjustments. Change-Id: Icbf088ce4c907e207f6f5d11b8bf5556fe2c90d6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61414 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 1 insertion(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index acb9286..4982384 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -77,13 +77,7 @@ register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true" - # Storage (SATA/SDCARD/EMMC) related UPDs - register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" @@ -155,8 +149,6 @@ device pci 16.0 hidden end # Management Engine Interface 1 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C4 device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf088ce4c907e207f6f5d11b8bf5556fe2c90d6 Gerrit-Change-Number: 61414 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Forbid FSP from disabling HECI1
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61455 ) Change subject: soc/intel/cannonlake: Forbid FSP from disabling HECI1 ...................................................................... soc/intel/cannonlake: Forbid FSP from disabling HECI1 The functionality of disabling HECI1 device has been moved from the FSP to coreboot (using `DISABLE_HECI1_AT_PRE_BOOT` config), hence, always set the `Heci1Disabled` UPD to `0`. BUG=none TEST=Boot to OS, verify HECI1 is disabled on hatch system using coreboot when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61455 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 6 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index af356d1..1726cd7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -586,9 +586,12 @@ params->ScsUfsEnabled = is_devfn_enabled(PCH_DEVFN_UFS); params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3); -#if !CONFIG(HECI_DISABLE_USING_SMM) - params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); -#endif + /* + * coreboot will handle disabling of HECI1 device if `DISABLE_HECI1_AT_PRE_BOOT` + * config is selected hence, don't let FSP to disable the HECI1 device and set + * the `Heci1Disabled` UPD to `0`. + */ + params->Heci1Disabled = 0; params->Device4Enable = config->Device4Enable; /* Teton Glacier hybrid storage support */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Gerrit-Change-Number: 61455 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configuration
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61570 to look at the new patch set (#2). Change subject: soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configuration ...................................................................... soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configuration I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the existing I2C pad control registers the bit definitions are different, so add a separate function to configure those pads which however still has the same function signature and is compatible with same data structs used for the devicetree settings. PPR #57243 Rev 1.50 was used as a reference. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 --- M src/soc/amd/common/block/i2c/Kconfig M src/soc/amd/common/block/i2c/Makefile.inc A src/soc/amd/common/block/i2c/i23c_pad_ctrl.c A src/soc/amd/common/block/i2c/i23c_pad_def.h M src/soc/amd/common/block/i2c/i2c_pad_def.h M src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/i2c.c 8 files changed, 140 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/61570/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 Gerrit-Change-Number: 61570 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61534 ) Change subject: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: it would likely be good to port this and the next patch forward to sabrina too -- To view, visit https://review.coreboot.org/c/coreboot/+/61534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Gerrit-Change-Number: 61534 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 13:46:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: add platform_v1 to reduce common ifd tool change
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61576 ) Change subject: util/ifdtool: add platform_v1 to reduce common ifd tool change ...................................................................... Patch Set 1: (1 comment) File util/ifdtool/ifdtool.c: https://review.coreboot.org/c/coreboot/+/61576/comment/2233428c_a64bb63a PS1, Line 227: PLATFORM_V1 PLATFORM_IFD2 is more applicable as all newer SoC might support IFDv2 instead v1 hence it is more applicable in IMO. @Edward, WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/61576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22 Gerrit-Change-Number: 61576 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 13:25:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd: Use madt_ioapic_from_hw()
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55571 ) Change subject: [WIP] soc/amd: Use madt_ioapic_from_hw() ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/stoneyridge/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139870): https://review.coreboot.org/c/coreboot/+/55571/comment/2fecacaf_a9d9d0a1 PS7, Line 34: current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Gerrit-Change-Number: 55571 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 13:08:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix vbt loading error
by Maulik V Vaghela (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Subrata Banik, Christian Walter, Meera Ravindranath, Angel Pons, Lean Sheng Tan. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61528 ) Change subject: mb/intel/adlrvp: Fix vbt loading error ...................................................................... Patch Set 4: (1 comment) File src/mainboard/intel/adlrvp/mainboard.c: https://review.coreboot.org/c/coreboot/+/61528/comment/786d70fe_68bba1fa PS2, Line 70: const char *mainboard_vbt_filename(void) > thanks Subrata. Done. […] @Sheng, chrome emerge has ability to add multiple files into CBFS using CBFS commands just before signing the image. Issue here is we can't statically decide how many VBT files we need to have during coreboot build. so as Nico pointed out, we may need to use site-local to overcome this issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/61528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Gerrit-Change-Number: 61528 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 12:48:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55311 ) Change subject: sb,soc/intel: Use acpi_create_madt_ioapic_from_hw() ...................................................................... Patch Set 9: Verified+1 (2 comments) File src/mainboard/aopen/dxplplusu/acpi_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139862): https://review.coreboot.org/c/coreboot/+/55311/comment/fd7ba3da_fbf16687 PS9, Line 31: current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139862): https://review.coreboot.org/c/coreboot/+/55311/comment/7e02e728_179bf3b9 PS9, Line 39: current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Gerrit-Change-Number: 55311 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 12:40:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd: Use madt_ioapic_from_hw()
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55571 to look at the new patch set (#7). Change subject: [WIP] soc/amd: Use madt_ioapic_from_hw() ...................................................................... [WIP] soc/amd: Use madt_ioapic_from_hw() Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/acpi.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/northbridge.c 9 files changed, 16 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/55571/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Gerrit-Change-Number: 55571 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2022