coreboot-gerrit February 2022

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Change in coreboot[master]: util/ifdtool: add platform_v1 to reduce common ifd tool change
by Wonkyu Kim (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Ethan Tsao, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Edward O'Callaghan. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61576 ) Change subject: util/ifdtool: add platform_v1 to reduce common ifd tool change ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This is in my list to do a better design where we don't need to pass the `platform name` from SoC. […] Yes and we also want to reduce change for supporting new platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/61576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22 Gerrit-Change-Number: 61576 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 08:39:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: add platform_v1 to reduce common ifd tool change
by Wonkyu Kim (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Ethan Tsao, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Edward O'Callaghan. Wonkyu Kim has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/61576 ) Change subject: util/ifdtool: add platform_v1 to reduce common ifd tool change ...................................................................... Removed cc Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/61576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22 Gerrit-Change-Number: 61576 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61550 to look at the new patch set (#6). Change subject: payloads/tianocore: Rework Makefile ...................................................................... payloads/tianocore: Rework Makefile Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This includes 3 new options: * TIANOCORE_BOOT_MANAGER_ESCAPE * TIANOCORE_HAVE_EFI_SHELL * TIANOCORE_FOLLOW_BGRT_SPEC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 145 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61550/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: add platform_v1 to reduce common ifd tool change
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Wonkyu Kim, Edward O'Callaghan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61576 ) Change subject: util/ifdtool: add platform_v1 to reduce common ifd tool change ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This is in my list to do a better design where we don't need to pass the `platform name` from SoC. I can understand you have problem releasing new SOC name early. -- To view, visit https://review.coreboot.org/c/coreboot/+/61576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22 Gerrit-Change-Number: 61576 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 08:16:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Retype variables
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58697 ) Change subject: cpu/x86/smm: Retype variables ...................................................................... cpu/x86/smm: Retype variables Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58697 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 3 files changed, 44 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index acbe579..888c97f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -777,7 +777,7 @@ if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 0); - if (smm_setup_relocation_handler((void *)perm_smbase, &smm_params)) { + if (smm_setup_relocation_handler(perm_smbase, &smm_params)) { printk(BIOS_ERR, "%s: smm setup failed\n", __func__); return CB_ERR; } @@ -813,7 +813,7 @@ printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase); - if (smm_load_module((void *)smbase, smsize, &smm_params)) + if (smm_load_module(smbase, smsize, &smm_params)) return CB_ERR; adjust_smm_apic_id_map(&smm_params); diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 101b7c5..ba179ca 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -243,10 +243,10 @@ * Place stacks in base -> base + size region, but ensure the stacks don't * overlap the staggered entry points. */ -static void *smm_stub_place_stacks(char *base, struct smm_loader_params *params) +static uintptr_t smm_stub_place_stacks(const uintptr_t base, struct smm_loader_params *params) { size_t total_stack_size; - char *stacks_top; + uintptr_t stacks_top; /* If stack space is requested assume the space lives in the lower * half of SMRAM. */ @@ -258,11 +258,11 @@ /* There has to be at least one stack user. */ if (params->num_concurrent_stacks < 1) - return NULL; + return 0; /* Stacks extend down to SMBASE */ - stacks_top = &base[total_stack_size]; - printk(BIOS_DEBUG, "%s: exit, stack_top %p\n", __func__, stacks_top); + stacks_top = base + total_stack_size; + printk(BIOS_DEBUG, "%s: exit, stack_top %lx\n", __func__, stacks_top); return stacks_top; } @@ -312,17 +312,17 @@ * by the permanent handler can be used during relocation. This is done via the * smram_start argument. */ -static int smm_module_setup_stub(void *const smbase, const size_t smm_size, +static int smm_module_setup_stub(const uintptr_t smbase, const size_t smm_size, struct smm_loader_params *params, void *const fxsave_area, - void *const smram_start) + const uintptr_t smram_start) { size_t total_save_state_size; size_t smm_stub_size; - char *smm_stub_loc; - void *stacks_top; + uintptr_t smm_stub_loc; + uintptr_t stacks_top; size_t size; - char *base; + uintptr_t base; size_t i; struct smm_stub_params *stub_params; struct rmodule smm_stub; @@ -368,11 +368,10 @@ return -1; } - smm_stub_loc = NULL; smm_stub_size = rmodule_memory_size(&smm_stub); /* Put the stub at the main entry point */ - smm_stub_loc = &base[SMM_ENTRY_OFFSET]; + smm_stub_loc = base + SMM_ENTRY_OFFSET; /* Stub is too big to fit. */ if (smm_stub_size > (size - SMM_ENTRY_OFFSET)) { @@ -385,18 +384,18 @@ * of SMRAM which is TSEG base */ stacks_top = smm_stub_place_stacks(smram_start, params); - if (stacks_top == NULL) { + if (stacks_top == 0) { printk(BIOS_ERR, "%s: error assigning stacks\n", __func__); return -1; } params->stack_top = stacks_top; /* Load the stub. */ - if (rmodule_load(smm_stub_loc, &smm_stub)) { + if (rmodule_load((void *)smm_stub_loc, &smm_stub)) { printk(BIOS_ERR, "%s: load module failed\n", __func__); return -1; } - if (!smm_stub_place_staggered_entry_points(base, params, &smm_stub)) { + if (!smm_stub_place_staggered_entry_points((void *)base, params, &smm_stub)) { printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); return -1; } @@ -429,7 +428,7 @@ /* Allow the initiator to manipulate SMM stub parameters. */ params->stub_params = stub_params; - printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p\n", + printk(BIOS_DEBUG, "SMM Module: stub loaded at %lx. Will call %p\n", smm_stub_loc, params->handler); return 0; } @@ -440,9 +439,9 @@ * assumption is that the stub will be entered from the default SMRAM * location: 0x30000 -> 0x40000. */ -int smm_setup_relocation_handler(void * const perm_smram, struct smm_loader_params *params) +int smm_setup_relocation_handler(const uintptr_t perm_smram, struct smm_loader_params *params) { - void *smram = (void *)(SMM_DEFAULT_BASE); + uintptr_t smram = SMM_DEFAULT_BASE; printk(BIOS_SPEW, "%s: enter\n", __func__); /* There can't be more than 1 concurrent save state for the relocation * handler because all CPUs default to 0x30000 as SMBASE. */ @@ -489,7 +488,8 @@ * expects a region large enough to encompass the handler and stacks * as well as the SMM_DEFAULT_SIZE. */ -int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) +int smm_load_module(const uintptr_t smram_base, const size_t smram_size, + struct smm_loader_params *params) { struct rmodule smm_mod; struct smm_runtime *handler_mod_params; @@ -500,16 +500,16 @@ size_t fxsave_size; void *fxsave_area; size_t total_size = 0; - char *base; - void *smram_start = smram; - if (size <= SMM_DEFAULT_SIZE) + uintptr_t base; /* The base for the permanent handler */ + + if (smram_size <= SMM_DEFAULT_SIZE) return -1; /* Load main SMI handler at the top of SMRAM * everything else will go below */ - base = smram; - base += size; + base = smram_base; + base += smram_size; /* Fail if can't parse the smm rmodule. */ if (rmodule_parse(&_binary_smm_start, &smm_mod)) @@ -517,13 +517,13 @@ /* Clear SMM region */ if (CONFIG(DEBUG_SMI)) - memset(smram, 0xcd, size); + memset((void *)smram_base, 0xcd, smram_size); total_stack_size = params->per_cpu_stack_size * params->num_concurrent_stacks; total_size += total_stack_size; /* Stacks are the base of SMRAM */ - params->stack_top = smram + total_stack_size; + params->stack_top = smram_base + total_stack_size; /* MSEG starts at the top of SMRAM and works down */ if (CONFIG(STM)) { @@ -534,7 +534,7 @@ /* FXSAVE goes below MSEG */ if (CONFIG(SSE)) { fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; - fxsave_area = base - fxsave_size; + fxsave_area = (char *)base - fxsave_size; base -= fxsave_size; total_size += fxsave_size; } else { @@ -546,8 +546,7 @@ base -= handler_size; total_size += handler_size; module_alignment = rmodule_load_alignment(&smm_mod); - alignment_size = module_alignment - - ((uintptr_t)base % module_alignment); + alignment_size = module_alignment - (base % module_alignment); if (alignment_size != module_alignment) { handler_size += alignment_size; base += alignment_size; @@ -555,10 +554,10 @@ printk(BIOS_DEBUG, "%s: total_smm_space_needed %zx, available -> %zx\n", - __func__, total_size, size); + __func__, total_size, smram_size); /* Does the required amount of memory exceed the SMRAM region size? */ - if (total_size > size) { + if (total_size > smram_size) { printk(BIOS_ERR, "%s: need more SMRAM\n", __func__); return -1; } @@ -568,22 +567,20 @@ return -1; } - if (rmodule_load(base, &smm_mod)) + if (rmodule_load((void *)base, &smm_mod)) return -1; params->handler = rmodule_entry(&smm_mod); handler_mod_params = rmodule_parameters(&smm_mod); - handler_mod_params->smbase = (uintptr_t)smram; - handler_mod_params->smm_size = size; + handler_mod_params->smbase = smram_base; + handler_mod_params->smm_size = smram_size; handler_mod_params->save_state_size = params->real_cpu_save_state_size; handler_mod_params->num_cpus = params->num_concurrent_stacks; handler_mod_params->gnvs_ptr = (uintptr_t)acpi_get_gnvs(); - printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", - __func__, smram); - printk(BIOS_DEBUG, "%s: smram_end: %p\n", - __func__, smram + size); - printk(BIOS_DEBUG, "%s: stack_top: %p\n", + printk(BIOS_DEBUG, "%s: smram_start: 0x%lx\n", __func__, smram_base); + printk(BIOS_DEBUG, "%s: smram_end: %lx\n", __func__, smram_base + smram_size); + printk(BIOS_DEBUG, "%s: stack_top: %lx\n", __func__, params->stack_top); printk(BIOS_DEBUG, "%s: handler start %p\n", __func__, params->handler); @@ -610,10 +607,9 @@ * will be staggered below */ base -= SMM_CODE_SEGMENT_SIZE; - printk(BIOS_DEBUG, "%s: cpu0 entry: %p\n", - __func__, base); + printk(BIOS_DEBUG, "%s: cpu0 entry: %lx\n", __func__, base); - if (!smm_create_map((uintptr_t)base, params->num_concurrent_save_states, params)) { + if (!smm_create_map(base, params->num_concurrent_save_states, params)) { printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); return -1; } @@ -623,5 +619,5 @@ cpus[i].ss_start + params->per_cpu_save_state_size; } - return smm_module_setup_stub(base, size, params, fxsave_area, smram_start); + return smm_module_setup_stub(base, smram_size, params, fxsave_area, smram_base); } diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 08404d0..848996f 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -135,7 +135,7 @@ * handle sparse APIC id space. */ struct smm_loader_params { - void *stack_top; + uintptr_t stack_top; size_t per_cpu_stack_size; size_t num_concurrent_stacks; @@ -149,8 +149,8 @@ }; /* Both of these return 0 on success, < 0 on failure. */ -int smm_setup_relocation_handler(void * const perm_smram, struct smm_loader_params *params); -int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); +int smm_setup_relocation_handler(const uintptr_t perm_smram, struct smm_loader_params *params); +int smm_load_module(uintptr_t smram_base, size_t smram_size, struct smm_loader_params *params); u32 smm_get_cpu_smbase(unsigned int cpu_num); -- To view, visit https://review.coreboot.org/c/coreboot/+/58697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Gerrit-Change-Number: 58697 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Reka Norman (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Krishna P Bhat D. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb: https://review.coreboot.org/c/coreboot/+/61141/comment/15e518fb_8bdc3118 PS5, Line 34: " Should we also configure the AUX DC bias pads here: ``` register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" ``` IIUC, this is needed for Type-C ports which don't have a retimer. On brya, most ports do, so it's configured per-variant. But on nissa, I assume most boards won't use retimers (right?), so should we configure it in the baseboard? -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 6 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 06:56:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by HAOUAS Elyes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth. HAOUAS Elyes has removed Julius Werner from this change. ( https://review.coreboot.org/c/coreboot/+/61533 ) Change subject: [only for test] test gcc-12 snapshot ...................................................................... Removed reviewer Julius Werner. -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by HAOUAS Elyes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61533 ) Change subject: [only for test] test gcc-12 snapshot ...................................................................... Patch Set 1: (1 comment) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/61533/comment/b23133a7_c4fdff3b PS1, Line 53: https://gcc.gnu.org/pub/gcc/snapshots/LATEST- > I added this URL into the allow-list for jenkins to download. […] Thank you :) I think gcc-11 will not like the new flag "-Wno-array-compare" (This is only to check if gcc-12 have the same issue as https://review.coreboot.org/c/coreboot/+/59636 ) -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 06:02:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Reka Norman (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Krishna P Bhat D. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb: https://review.coreboot.org/c/coreboot/+/61141/comment/91e9f18e_7ea8e7f5 PS5, Line 28: > I think WFC won't be a major choice in variants, so prefer to hand it over to variants. Makes sense. -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 6 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 05:58:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Kangheui Won (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Krishna P Bhat D. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... Patch Set 6: (3 comments) File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb: https://review.coreboot.org/c/coreboot/+/61141/comment/a01d8c2f_fdbfef2d PS5, Line 28: > Port 7 (index 6) is actually used for WFC on nereid. […] I think WFC won't be a major choice in variants, so prefer to hand it over to variants. https://review.coreboot.org/c/coreboot/+/61141/comment/7484c77d_00de9c1e PS5, Line 120: i2c0 > Can we add the tpm driver here? I think the only reason brya has it in the variants is that some var […] Yep let's encourage variants not to change i2c bus for the tpm. https://review.coreboot.org/c/coreboot/+/61141/comment/e6dce3c7_e9b92108 PS5, Line 123: pcie_rp7 > Are we supporting RTD3 on the SD card, and if so should we add the RTD3 driver here? On brya, the SD […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 6 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 05:47:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2022