coreboot-gerrit February 2022

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Change in qc_blobs[master]: sc7280/boot/shrm: Update qclib blobs binaries and release notes versi...
by Sudheer Amrabadi (Code Review) 03 Feb '22

03 Feb '22

Sudheer Amrabadi has uploaded this change for review. ( https://review.coreboot.org/c/qc_blobs/+/61590 ) Change subject: sc7280/boot/shrm: Update qclib blobs binaries and release notes version from 20 to 23 ...................................................................... sc7280/boot/shrm: Update qclib blobs binaries and release notes version from 20 to 23 Change-Id: Ia53a0818e4c82301151caf86d846c98575857bc7 --- M sc7280/boot/Pmic.bin M sc7280/boot/QcLib.elf M sc7280/boot/Release_Notes.txt M sc7280/shrm/Release_Notes.txt M sc7280/shrm/shrm.elf 5 files changed, 57 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/90/61590/1 diff --git a/sc7280/boot/Pmic.bin b/sc7280/boot/Pmic.bin index 25a65b4..211aa92 100644 --- a/sc7280/boot/Pmic.bin +++ b/sc7280/boot/Pmic.bin Binary files differ diff --git a/sc7280/boot/QcLib.elf b/sc7280/boot/QcLib.elf index 423dffc..1b5d2cb 100644 --- a/sc7280/boot/QcLib.elf +++ b/sc7280/boot/QcLib.elf Binary files differ diff --git a/sc7280/boot/Release_Notes.txt b/sc7280/boot/Release_Notes.txt index 0718f2b..aa19884 100644 --- a/sc7280/boot/Release_Notes.txt +++ b/sc7280/boot/Release_Notes.txt @@ -1,3 +1,24 @@ +================== Release 00023 ================================ +This Release Notes file covers these blobs: + * dcb.bin + * Pmic.bin + * QcLib.elf + +Version : 00023 + +Release Date : Feb, 2022 + +Supported Silicon : SC7280 + +Changes since last version: + * KPDPWR interrupt set to Falling Edge triggered. + +Above Bins were used to generate coreboot image. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report ================== Release 00020 ================================ This Release Notes file covers these blobs: * dcb.bin diff --git a/sc7280/shrm/Release_Notes.txt b/sc7280/shrm/Release_Notes.txt index 82559d5..aa19884 100644 --- a/sc7280/shrm/Release_Notes.txt +++ b/sc7280/shrm/Release_Notes.txt @@ -1,6 +1,29 @@ +================== Release 00023 ================================ +This Release Notes file covers these blobs: + * dcb.bin + * Pmic.bin + * QcLib.elf + +Version : 00023 + +Release Date : Feb, 2022 + +Supported Silicon : SC7280 + +Changes since last version: + * KPDPWR interrupt set to Falling Edge triggered. + +Above Bins were used to generate coreboot image. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report ================== Release 00020 ================================ This Release Notes file covers these blobs: - * shrm.elf + * dcb.bin + * Pmic.bin + * QcLib.elf Version : 00020 @@ -20,8 +43,10 @@ ================== Release 00016 ================================ This Release Notes file covers these blobs: - * shrm.elf - + * dcb.bin + * Pmic.bin + * QcLib.elf + Version : 00016 Release Date : Oct, 2021 @@ -40,8 +65,10 @@ ================== Release 00013 ================================ This Release Notes file covers these blobs: - * shrm.elf - + * dcb.bin + * Pmic.bin + * QcLib.elf + Version : 00013 Release Date : Sep, 2021 @@ -61,8 +88,10 @@ ================== Release 741 ================================ This Release Notes file covers these blobs: - * shrm.elf - + * dcb.bin + * Pmic.bin + * QcLib.elf + Version : 000741 Release Date : April, 2021 diff --git a/sc7280/shrm/shrm.elf b/sc7280/shrm/shrm.elf index 57666a0..2204f86 100644 --- a/sc7280/shrm/shrm.elf +++ b/sc7280/shrm/shrm.elf Binary files differ -- To view, visit https://review.coreboot.org/c/qc_blobs/+/61590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: Ia53a0818e4c82301151caf86d846c98575857bc7 Gerrit-Change-Number: 61590 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/apollolake: Add northbridge that avoids collisions
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61589 ) Change subject: soc/apollolake: Add northbridge that avoids collisions ...................................................................... soc/apollolake: Add northbridge that avoids collisions Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3c69b7cfd4c160a5d5b827c45a99abe963b9f7dd --- A src/soc/intel/apollolake/acpi/northbridge-glk.asl A src/soc/intel/apollolake/acpi/pdrc.asl 2 files changed, 392 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61589/1 diff --git a/src/soc/intel/apollolake/acpi/northbridge-glk.asl b/src/soc/intel/apollolake/acpi/northbridge-glk.asl new file mode 100644 index 0000000..d52ffe9 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/northbridge-glk.asl @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Name(_HID, EISAID("PNP0A08")) /* PCIe */ +Name(_CID, EISAID("PNP0A03")) /* PCI */ + +Device(MCHC) +{ + Name(_ADR, 0x00000000) + OperationRegion(HBUS, PCI_Config, 0x00, 0xFF) + Field(HBUS, DWordAcc, NoLock, Preserve) + { + Offset(0x48), + MHEN, 1, + , 14, + MHBR, 24, + Offset(0xB0), + BDSM, 32, + Offset(0xBC), + TOLD, 32, + } +} + +Name (MAB, 0x1000000000000) +Name (MAL, 0x1000000000000) +Name (MAM, 0x1000000000000) + +Method(_CRS,0,Serialized) { + Name (MCRS, ResourceTemplate() + { + WordBusNumber ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + 0x0000, + 0x0000, + 0x00FF, + 0x0000, + 0x0100 + ) + + Io (Decode16, 0x70, 0x77, 0x01, 0x08) + Io (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) + + DWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0000, + 0x006F, + 0x0000, + 0x0070 + ) + + DWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0078, + 0x0CF7, + 0x0000, + 0x0C80 + ) + + DWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0D00, + 0xFFFF, + 0x0000, + 0xF300 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000A0000, + 0x000BFFFF, + 0x00000000, + 0x00020000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000C0000, + 0x000DFFFF, + 0x00000000, + 0x00020000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000E0000, + 0x000FFFFF, + 0x00000000, + 0x00020000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x3be00000, + 0x3FFFFFFF, + 0x00000000, + 0x04200000 + ,,, + STOM + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0x80000000, + 0xBFFFFFFF, + 0x00000000, + 0x40000000 + ,,, + PM01 + ) + + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xE0000000, + 0xEFFFFFFF, + 0x00000000, + 0x10000000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFEA00000, + 0xFEAFFFFF, + 0x00000000, + 0x00100000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED00000, + 0xFED003FF, + 0x00000000, + 0x00000400 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED01000, + 0xFED01FFF, + 0x00000000, + 0x00001000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED03000, + 0xFED03FFF, + 0x00000000, + 0x00001000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED06000, + 0xFED06FFF, + 0x00000000, + 0x00001000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED08000, + 0xFED09FFF, + 0x00000000, + 0x00002000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED80000, + 0xFEDBFFFF, + 0x00000000, + 0x00040000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0xFED1C000 , + 0xFED1CFFF, + 0x00000000, + 0x00001000 + ) + + DWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadOnly, + 0x00000000, + 0xFEE00000, + 0xFEEFFFFF, + 0x00000000, + 0x00100000 + ) + + QWordMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x00000000, + 0x000000000, + 0x000000000, + 0x00000000, + 0x000000000 + ,,, + PM03 + ) + }) + + CreateDwordField(MCRS, PM01._MIN, PMIN) + CreateDwordField(MCRS, PM01._MAX, PMAX) + CreateDwordField(MCRS, PM01._LEN, PLEN) + + Store (A4GS, PLEN) + Store (A4GB, PMIN) + Subtract (Add (PMIN, PLEN), 1, PMAX) + + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) + + Store(^MCHC.BDSM, GMIN) + + And(^MCHC.TOLD, 0xFFFFF000, GMAX) + Decrement(GMAX) + + Add(Subtract(GMAX, GMIN), 1, GLEN) + + CreateQwordField(MCRS, PM03._LEN, MMIN) + CreateQwordField(MCRS, PM03._MIN, MMAX) + CreateQwordField(MCRS, PM03._MAX, MLEN) + Store(MAB, MMAX) + Store(MAM, MLEN) + Store(MAL, MMIN) + + Return(MCRS) +} + +#include "pdrc.asl" + +/* GFX 00:02.0 */ +#include <drivers/intel/gma/acpi/gfx.asl> diff --git a/src/soc/intel/apollolake/acpi/pdrc.asl b/src/soc/intel/apollolake/acpi/pdrc.asl new file mode 100644 index 0000000..c7bcb03 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pdrc.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () + { + /* PCIEX BAR */ + Memory32Fixed (ReadWrite, 0x0e0000000, 0x010000000, PCIX) + + /* MPHY BAR */ + Memory32Fixed (ReadWrite, 0x0fea00000, 0x0100000, MPHB) + + /* SPI BAR */ + Memory32Fixed (ReadWrite, 0x0fed01000, 0x01000, SPIB) + + /* PMC BAR */ + Memory32Fixed (ReadWrite, 0x0fed03000, 0x01000, PMCB) + + /* PUNIT BAR */ + Memory32Fixed (ReadWrite, 0x0fed06000, 0x01000, PUNB) + + /* ILB BAR */ + Memory32Fixed (ReadWrite, 0x0fed08000, 0x02000, ILBB) + + /* IO BAR */ + Memory32Fixed (ReadWrite, 0x0fed80000, 0x040000, IOBR) + + /* RCRB BAR */ + Memory32Fixed (ReadWrite, 0x0fed1c000, 0x01000, RCRB) + + /* Local APIC range */ + Memory32Fixed (ReadOnly, 0x0fee00000, 0x0100000, LIOH) + }) + + Return (BUF0) + } +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/61589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c69b7cfd4c160a5d5b827c45a99abe963b9f7dd Gerrit-Change-Number: 61589 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mp_init.c: Rename num_concurrent_stacks
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Angel Pons, Arthur Heymans, Kyösti Mälkki. Kyösti Mälkki has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58699 ) Change subject: cpu/x86/mp_init.c: Rename num_concurrent_stacks ...................................................................... cpu/x86/mp_init.c: Rename num_concurrent_stacks This is just the amount of cpus so rename it for simplicity. Change-Id: Ib2156136894eeda4a29e8e694480abe06da62959 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 3 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58699/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2156136894eeda4a29e8e694480abe06da62959 Gerrit-Change-Number: 58699 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Improve smm stack setup
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kyösti Mälkki. Kyösti Mälkki has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58698 ) Change subject: cpu/x86/smm: Improve smm stack setup ...................................................................... cpu/x86/smm: Improve smm stack setup Both the relocation handler and the permanent handler use the same stacks, so things can be simplified. Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/mp.h M src/include/cpu/x86/smm.h 4 files changed, 47 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58698/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Gerrit-Change-Number: 58698 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61588 ) Change subject: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function ...................................................................... soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function This patch removes `gpios_to_lock` lists and `soc_gpio_lock_config` override function from Alder Lake SoC as the required config (SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) to perform GPIO PAD lock configuration using SMM is not enabled. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8 --- M src/soc/intel/alderlake/gpio.c 1 file changed, 0 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61588/1 diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index bf067b2..dc5847d 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -265,60 +265,3 @@ *num = ARRAY_SIZE(routes); return routes; }; - -/* GPIOs controllable by non-host (x86) agent, eg. ISH, THC, etc */ -static const struct gpio_lock_config gpios_to_lock[] = { - { GPP_A16, GPIO_LOCK_CONFIG }, /* ISH_GP5 NF4 */ - { GPP_B3, GPIO_LOCK_CONFIG }, /* ISH_GP4B NF4 (not avail in ADL PCH-M) */ - { GPP_B4, GPIO_LOCK_CONFIG }, /* ISH_GP5B NF4 (not avail in ADL PCH-M) */ - { GPP_B5, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SDA NF1 */ - { GPP_B6, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SCL NF1 */ - { GPP_B7, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SDA NF1 */ - { GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */ - { GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */ - { GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */ - { GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */ - { GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */ - { GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */ - { GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */ - { GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */ - { GPP_D3, GPIO_LOCK_CONFIG }, /* ISH_GP3 NF1 */ - { GPP_D9, GPIO_LOCK_CONFIG }, /* ISH_SPI_CS# NF1 */ - { GPP_D10, GPIO_LOCK_CONFIG }, /* ISH_SPI_CLK NF1 */ - { GPP_D11, GPIO_LOCK_CONFIG }, /* ISH_SPI_MISO NF1 */ - { GPP_D12, GPIO_LOCK_CONFIG }, /* ISH_SPI_MOSI NF1 */ - { GPP_D13, GPIO_LOCK_CONFIG }, /* ISH_UART0_RXD NF1 */ - { GPP_D14, GPIO_LOCK_CONFIG }, /* ISH_UART0_TXD NF1 */ - { GPP_D15, GPIO_LOCK_CONFIG }, /* ISH_UART0_RTS# NF1 */ - { GPP_D16, GPIO_LOCK_CONFIG }, /* ISH_UART0_CTS# NF1 */ - { GPP_D17, GPIO_LOCK_CONFIG }, /* ISH_UART1_RXD NF2 */ - { GPP_D18, GPIO_LOCK_CONFIG }, /* ISH_UART1_TXD NF2 */ - { GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */ - { GPP_H12, GPIO_LOCK_CONFIG }, /* ISH_GP6B NF4 */ - { GPP_H13, GPIO_LOCK_CONFIG }, /* ISH_GP7B NF4 */ - - { GPP_E1, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO2 NF2 */ - { GPP_E2, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO3 NF2 */ - { GPP_E6, GPIO_LOCK_CONFIG }, /* THC0_SPI1_RST# NF2 */ - { GPP_E10, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CS# NF2 */ - { GPP_E11, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CLK NF2 */ - { GPP_E12, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO1 NF2 */ - { GPP_E13, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO0 NF2 */ - { GPP_E17, GPIO_LOCK_CONFIG }, /* THC0_SPI1_INT# NF2 */ - { GPP_F11, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CLK NF3 */ - { GPP_F12, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO0 NF3 */ - { GPP_F13, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO1 NF3 */ - { GPP_F14, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO2 NF3 */ - { GPP_F15, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO3 NF3 */ - { GPP_F16, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CS# NF3 */ - { GPP_F17, GPIO_LOCK_CONFIG }, /* THC1_SPI2_RST# NF3 */ - { GPP_F18, GPIO_LOCK_CONFIG }, /* THC1_SPI2_INT# NF3 */ - - { GPP_H3, GPIO_LOCK_CONFIG }, /* SX_EXIT_HOLDOFF# NF1 */ -}; - -const struct gpio_lock_config *soc_gpio_lock_config(size_t *num) -{ - *num = ARRAY_SIZE(gpios_to_lock); - return gpios_to_lock; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/61588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8 Gerrit-Change-Number: 61588 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Remove GPIO PAD lock config override from mainboard
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61587 to look at the new patch set (#2). Change subject: soc/intel/common: Remove GPIO PAD lock config override from mainboard ...................................................................... soc/intel/common: Remove GPIO PAD lock config override from mainboard This patch removes mainboard capability to override GPIO PAD lock configuration using `mb_gpio_lock_config` override function as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 --- M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/61587/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 Gerrit-Change-Number: 61587 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Remove GPIO PAD lock config override from mainboard
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61587 ) Change subject: soc/intel/common: Remove GPIO PAD lock config override from mainboard ...................................................................... soc/intel/common: Remove GPIO PAD lock config override from mainboard This patch removes mainboard capability to override GPIO PAD lock configuration using `mb_gpio_lock_config` override function as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 --- M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/61587/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index b37dd12..d5cc8fe 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -260,12 +260,6 @@ const struct gpio_lock_config *soc_gpio_lock_config(size_t *num); /* - * Returns an array of gpio_lock_config entries that the mainboard - * deems security risks that should be locked down. - */ -const struct gpio_lock_config *mb_gpio_lock_config(size_t *num); - -/* * Returns the pmc_gpe to gpio_gpe mapping table * */ diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 32de2f6..8d20d55 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -317,32 +317,18 @@ return NULL; } -__weak const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) -{ - *num = 0; - return NULL; -} - static void soc_lock_gpios(void) { const struct gpio_lock_config *soc_gpios; const struct gpio_lock_config *mb_gpios; size_t soc_gpio_num; - size_t mb_gpio_num; /* get list of gpios from SoC */ soc_gpios = soc_gpio_lock_config(&soc_gpio_num); - /* get list of gpios from mainboard */ - mb_gpios = mb_gpio_lock_config(&mb_gpio_num); - /* Lock any soc requested gpios */ if (soc_gpio_num) gpio_lock_pads(soc_gpios, soc_gpio_num); - - /* Lock any mainboard requested gpios */ - if (mb_gpio_num) - gpio_lock_pads(mb_gpios, mb_gpio_num); } static void finalize(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/61587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 Gerrit-Change-Number: 61587 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Martin Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61550 to look at the new patch set (#7). Change subject: payloads/tianocore: Rework Makefile ...................................................................... payloads/tianocore: Rework Makefile Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This includes 3 new options: * TIANOCORE_BOOT_MANAGER_ESCAPE * TIANOCORE_HAVE_EFI_SHELL * TIANOCORE_FOLLOW_BGRT_SPEC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 148 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61550/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Remove `mb_gpio_lock_config()` override function
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61503 ) Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > Have we decided that the SoC will no longer manually lock gpios it deems sensitive, and instead leave that decision completley up to the mainboard? > > I got you point about having a provision where SoC code first performs GPIO programming like NF and then allow remaining GPIO override from mainboards ? > > Today we don't have provision for SoC code to perform GPIO programming/lock hence relying on mainboard to perform all GPIO programming. Additionally, isn't that is the right approach as well ? Assume a case where GPP_A5 is I2C0_SDL hence should be NF but chrome design don't have any device over I2C0 hence, can be available to pick GPP_A5 as GPIO instead. So, allowing SoC code to perform GPIO lock configuration might limit the freedom at mb side. > > WDYT? Also, please check below code, looks like `soc_lock_gpios()` is a dead code on ADL as we haven't selected SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config. https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… > > > > > If the answer is yes, then we could remove the soc_lock_gpios() in src/soc/intel/common/block/smm/smihandler.c, soc_gpio_lock_config() call in src/soc/intel/alderlake/gpio.c, and the associated prototypes. > > > > If the answer is no, we can still remove mb_gpio_lock_config(). -- To view, visit https://review.coreboot.org/c/coreboot/+/61503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Gerrit-Change-Number: 61503 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 10:00:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Improve smm stack setup
by Arthur Heymans (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58698 ) Change subject: cpu/x86/smm: Improve smm stack setup ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Does this need to be swapped with 'rename num_concurrent_stacks' ? -- To view, visit https://review.coreboot.org/c/coreboot/+/58698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Gerrit-Change-Number: 58698 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 09:54:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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