coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Kangheui Won (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Krishna P Bhat D. Hello build bot (Jenkins), Reka Norman, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61141 to look at the new patch set (#6). Change subject: mb/google/nissa: Add devicetree ...................................................................... mb/google/nissa: Add devicetree Fill in devicetree for nissa baseboard based on schematics. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb 1 file changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/61141/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 6 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot/secdata_tpm: Set up space for widevine counter info
by Name of user not set (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Andrey Pronin, Raul Rangel, Mohan Viswanathan, Jon Murphy, Paul Menzel, Julius Werner, Rob Barnes, Yu-Ping Wu, Karthik Ramasubramanian. Name of user not set #1004133 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61521 ) Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Sorry, I was more hoping for an exact struct layout or something. […] The additional non-volatile space is required to store the status of the counters in use. Although it can be done by reading them until we get a BAD_INDEX, Trusted Application can create and delete the counters dynamically. To keep track of the current counter status across reboot cycles, additional non-volatile space is required -- To view, visit https://review.coreboot.org/c/coreboot/+/61521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80de9024195452a235cbed73e21410f848c91722 Gerrit-Change-Number: 61521 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mohan Viswanathan Gerrit-CC: Name of user not set #1004133 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mohan Viswanathan Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 05:44:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mohan Viswanathan Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update Type-C USB2 port configuration correctly
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 ) Change subject: mb/google/brya: Update Type-C USB2 port configuration correctly ...................................................................... Patch Set 2: (15 comments) File src/soc/intel/alderlake/include/soc/usb.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/9dea5c27_fa19015c PS2, Line 120: .enable = 1, \ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/406fabba_57ac7789 PS2, Line 120: .enable = 1, \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/d472e047_baa58d79 PS2, Line 121: .ocpin = (pin), \ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/574d232e_032f5727 PS2, Line 121: .ocpin = (pin), \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/3826b755_1d3f6983 PS2, Line 122: .tx_bias = USB2_BIAS_56P3MV, \ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/b040cd56_d28df6dd PS2, Line 122: .tx_bias = USB2_BIAS_56P3MV, \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/17f7ab7e_e5e435a4 PS2, Line 123: .tx_emp_enable = USB2_PRE_EMP_ON, \ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/1402ec29_8e1936f6 PS2, Line 123: .tx_emp_enable = USB2_PRE_EMP_ON, \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/42795190_8982ab75 PS2, Line 124: .pre_emp_bias = USB2_BIAS_56P3MV, \ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/be0944df_4b1b7e25 PS2, Line 124: .pre_emp_bias = USB2_BIAS_56P3MV, \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/3e6f4765_80872cde PS2, Line 125: .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/0f80af13_b389a397 PS2, Line 125: .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/5ca253d8_cee154d5 PS2, Line 126: .type_c = 1, \ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/60b9b2bb_42e06952 PS2, Line 126: .type_c = 1, \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139838): https://review.coreboot.org/c/coreboot/+/61586/comment/a8eea41f_2bfdb2d1 PS2, Line 126: .type_c = 1, \ Avoid unnecessary line continuations -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 05:33:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update Type-C USB2 port configuration correctly
by Sridhar Siricilla (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61586 to look at the new patch set (#2). Change subject: mb/google/brya: Update Type-C USB2 port configuration correctly ...................................................................... mb/google/brya: Update Type-C USB2 port configuration correctly Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/soc/intel/alderlake/include/soc/usb.h 3 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by Martin Roth (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: HAOUAS Elyes. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61533 ) Change subject: [only for test] test gcc-12 snapshot ...................................................................... Patch Set 1: (1 comment) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/61533/comment/ec0205de_c3b6764b PS1, Line 53: https://gcc.gnu.org/pub/gcc/snapshots/LATEST- I added this URL into the allow-list for jenkins to download. For security, Jenkins will only download from specified locations, so when the URL changes, jenkins needs to be updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Feb 2022 04:52:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update Type-C USB2 port configuration correctly
by Sridhar Siricilla (Code Review) 03 Feb '22

03 Feb '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61586 ) Change subject: mb/google/brya: Update Type-C USB2 port configuration correctly ...................................................................... mb/google/brya: Update Type-C USB2 port configuration correctly Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/1 diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 23071fe..ea25742 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -32,7 +32,6 @@ register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 0dd8c75..5c208b6 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -32,7 +32,6 @@ register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cyan: Fixup variant GPIOs
by CoolStar Organization (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Matt DeVillier. CoolStar Organization has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61585 ) Change subject: mb/google/cyan: Fixup variant GPIOs ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: verified GPIO IRQ storm is fixed in Windows on both relm and cyan with these changes -- To view, visit https://review.coreboot.org/c/coreboot/+/61585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Gerrit-Change-Number: 61585 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar Organization <coolstarorganization(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 04:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Fixup variant GPIOs
by Matt DeVillier (Code Review) 03 Feb '22

03 Feb '22

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61585 ) Change subject: mb/google/cyan: Fixup variant GPIOs ...................................................................... mb/google/cyan: Fixup variant GPIOs - set GPSE-77 (Maxim jack detect) to NC for variants using Realtek audio - set GPSW-37 to NC for all variants (not used for LPE audio) - set GPSW-95 (Realtek jack detect) to NC for variant using Maxim audio - set GPSE-77 as maskable on variant using Maxim audio, to match mask setting for jack detect GPIO on other variants - set GPSE-81 as maskable on CELES to prevent interrupt storm (likely due to change in cherryview pinctrl driver circa kernel v3.18 which no longer masks all interrupts at init) Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c 11 files changed, 20 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/61585/1 diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index b2d1cbe..4e91db4 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index b385ad7..71e209e 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -51,12 +51,11 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, + GPI(trig_edge_both, L1, P_20K_H, maskable, en_edge_detect, NA, NA), /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr assumed gpio number */ @@ -92,8 +91,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 9491c25..5723acf 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -51,8 +51,8 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPI(trig_edge_both, L0, NA, 0, en_edge_detect, NA, NA), + /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +90,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ GPIO_NC, /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ @@ -124,8 +123,7 @@ assert it low. */ GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + GPIO_NC, /* 95 RTK_AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ GPIO_END diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index c1b43b8..d285c04 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 4e4b01a..23fe4e1 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index ece6c80..13cc639 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 5a0c13a..2d308f5 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index cdf57a4..c57d28c 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 11071eb..d2e79f1 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index cef45aa..ede6229 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 6e99330..3bb3931 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -51,8 +51,7 @@ GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Gerrit-Change-Number: 61585 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support
by Chris Wang (Code Review) 03 Feb '22

03 Feb '22

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61581 ) Change subject: mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support ...................................................................... mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support Add ID "AMDI5619" for machine driver to support ALC5682I-VS + ACL1019 combination. BUG=b:211835769 TEST=Build dewatt, codec is functional with new machine driver. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/61581/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index eb3d00d..6cb8293 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -4,6 +4,14 @@ device domain 0 on device ref gpp_bridge_1 off end # no SD device ref gpp_bridge_2 off end # no WWAN + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5619"" + device generic 0.0 on end + end + end # Audio + end end # domain register "slow_ppt_limit_mW" = "25000" -- To view, visit https://review.coreboot.org/c/coreboot/+/61581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b Gerrit-Change-Number: 61581 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Lock TPM pin in brask and brya baseboards
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61499 ) Change subject: mb/google/brya: Lock TPM pin in brask and brya baseboards ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/agah/gpio.c: https://review.coreboot.org/c/coreboot/+/61499/comment/9e5eac45_70621649 PS5, Line 37: /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ : PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), : /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ : PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), > These are already defined this way in variants/baseboard/brya/gpio.c, no need to duplicate here. Oh, I saw H6/H7 also exist in few variants https://review.coreboot.org/c/coreboot/+/61499/5/src/mainboard/google/brya/… > > Same holds true for the other files in this CL that add this configuration for GPP_B7 and GPP_B8, since all of the devices so far are brya variants (as opposed to brask variants). -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 03:29:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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