coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

1 participants
7066 discussions

Change in coreboot[master]: mb/google/brya: Remove `mb_gpio_lock_config()` override function
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61503 ) Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > Have we decided that the SoC will no longer manually lock gpios it deems sensitive, and instead leave that decision completley up to the mainboard? > > I got you point about having a provision where SoC code first performs GPIO programming like NF and then allow remaining GPIO override from mainboards ? > > Today we don't have provision for SoC code to perform GPIO programming/lock hence relying on mainboard to perform all GPIO programming. Additionally, isn't that is the right approach as well ? Assume a case where GPP_A5 is I2C0_SDL hence should be NF but chrome design don't have any device over I2C0 hence, can be available to pick GPP_A5 as GPIO instead. So, allowing SoC code to perform GPIO lock configuration might limit the freedom at mb side. > > WDYT? Also, please check below code, looks like `soc_lock_gpios()` is a dead code on ADL as we haven't selected SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config. https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… > > > > > If the answer is yes, then we could remove the soc_lock_gpios() in src/soc/intel/common/block/smm/smihandler.c, soc_gpio_lock_config() call in src/soc/intel/alderlake/gpio.c, and the associated prototypes. > > > > If the answer is no, we can still remove mb_gpio_lock_config(). -- To view, visit https://review.coreboot.org/c/coreboot/+/61503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Gerrit-Change-Number: 61503 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 10:00:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm: Improve smm stack setup
by Arthur Heymans (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58698 ) Change subject: cpu/x86/smm: Improve smm stack setup ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Does this need to be swapped with 'rename num_concurrent_stacks' ? -- To view, visit https://review.coreboot.org/c/coreboot/+/58698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Gerrit-Change-Number: 58698 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 09:54:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Remove `mb_gpio_lock_config()` override function
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61503 ) Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Have we decided that the SoC will no longer manually lock gpios it deems sensitive, and instead leave that decision completley up to the mainboard? I got you point about having a provision where SoC code first performs GPIO programming like NF and then allow remaining GPIO override from mainboards ? Today we don't have provision for SoC code to perform GPIO programming/lock hence relying on mainboard to perform all GPIO programming. Additionally, isn't that is the right approach as well ? Assume a case where GPP_A5 is I2C0_SDL hence should be NF but chrome design don't have any device over I2C0 hence, can be available to pick GPP_A5 as GPIO instead. So, allowing SoC code to perform GPIO lock configuration might limit the freedom at mb side. WDYT? > > If the answer is yes, then we could remove the soc_lock_gpios() in src/soc/intel/common/block/smm/smihandler.c, soc_gpio_lock_config() call in src/soc/intel/alderlake/gpio.c, and the associated prototypes. > > If the answer is no, we can still remove mb_gpio_lock_config(). -- To view, visit https://review.coreboot.org/c/coreboot/+/61503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Gerrit-Change-Number: 61503 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 09:41:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Arthur Heymans, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58700 ) Change subject: cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG ...................................................................... Patch Set 4: Code-Review+1 (2 comments) File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/58700/comment/1a19a7a5_c3a5340d PS2, Line 603: * +-----------------+ <- smram + size == 0x10000 > 0xb0000 ? Ack https://review.coreboot.org/c/coreboot/+/58700/comment/a52c7833_8e876d65 PS2, Line 613: * | stub code | <- cpu3, etc > Is MAX_CPUS=4 correct, remove ", etc" Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/58700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Gerrit-Change-Number: 58700 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Feb 2022 09:12:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm: Improve smm stack setup
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58698 ) Change subject: cpu/x86/smm: Improve smm stack setup ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Gerrit-Change-Number: 58698 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Feb 2022 09:10:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: configs/i440fx: Build-test PARALLEL_MP
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Angel Pons, Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59695 ) Change subject: configs/i440fx: Build-test PARALLEL_MP ...................................................................... Patch Set 6: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59695/comment/f4b3f456_5316145b PS1, Line 7: Buildtest > Build-test Done https://review.coreboot.org/c/coreboot/+/59695/comment/7e988613_bb8c1009 PS1, Line 7: i44fx > typo: i44*0*fx Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Gerrit-Change-Number: 59695 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Feb 2022 09:09:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58700 ) Change subject: cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG ...................................................................... cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG This will allow to migrate all platform to the parallel_mp init code and drop the old lapic_init code. Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smm_module_loader.c 3 files changed, 109 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/58700/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Gerrit-Change-Number: 58700 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: configs/i440fx: Build-test PARALLEL_MP
by Kyösti Mälkki (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59695 ) Change subject: configs/i440fx: Build-test PARALLEL_MP ...................................................................... configs/i440fx: Build-test PARALLEL_MP Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M configs/config.emulation_qemu_x86_i440fx_debug 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59695/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Gerrit-Change-Number: 59695 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Inject CSE TS into timestamp_table
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bora Guvendik, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59507 ) Change subject: soc/intel/alderlake: Inject CSE TS into timestamp_table ...................................................................... Patch Set 11: (3 comments) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/59507/comment/d89f4681_b1892544 PS11, Line 164: cse_get_telemetry_data(); if (CONFIG(SOC_INTEL_CSE_PERFORMANCE_TELEMETRY)) cse_get_telemetry_data(); You don't need that weak implementation above may be. File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/59507/comment/40cb8d92_ffcf3296 PS11, Line 149: SOC_INTEL_CSE_PERFORMANCE_TELEMETRY shouldn't we highlight as pre-cpu reset telemetry ? https://review.coreboot.org/c/coreboot/+/59507/comment/e386d6df_24fbec94 PS11, Line 151: SOC_INTEL_CSE_LITE_SKU are this feature only implemented for lite sku alone. for my knowledge -- To view, visit https://review.coreboot.org/c/coreboot/+/59507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Gerrit-Change-Number: 59507 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 08:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Subrata Banik (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 13: (4 comments) File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/61389/comment/db6162f3_8456f07f PS11, Line 122: printk(BIOS_INFO, "gfx memory bar(0x18) = 0x%lx GFX_MEMBASE_OFFSET = 0x%x\n", : memory_base, CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET); > The purpose of this message is to print gfx basic information without adding debug message and re-build while there is gfx issue. I don't think one need to relying on coreboot debug msg to know the GMADR address, PCI config read is sufficient. Also, if you have `zero` value in GMADR then the line #125 can able to catch such failure as well. File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/61389/comment/a81f45d8_419bdb37 PS13, Line 128: memory_base = memory_base + CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; you have marked done but appear not done yet. memory_base += CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; Also offline discussion with Will suggests me that this logic is memory_base += (GTT size + CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET); Are we ignoring GTT size or I misunderstood @Will ? https://review.coreboot.org/c/coreboot/+/61389/comment/af01a419_be8f0e5b PS13, Line 129: after shift what is shift ? https://review.coreboot.org/c/coreboot/+/61389/comment/3a775ad3_77711951 PS13, Line 129: printk(BIOS_INFO, "gfx memory base(after shift) = 0x%lx\n", memory_base); same as last comment, you don't need this. -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 13 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 08:49:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ethan Tsao <ethan.tsao(a)intel.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2022