coreboot-gerrit February 2022

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61259 to look at the new patch set (#9). Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... soc/amd/cezanne: Turn off gpp clock request for disabled devices The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled FIXED=b:202252869 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c --- M src/mainboard/google/guybrush/Makefile.inc M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 3 files changed, 82 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 9 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

1 0

Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61259 to look at the new patch set (#8). Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... soc/amd/cezanne: Turn off gpp clock request for disabled devices The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled FIXED=b:202252869 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c --- M src/mainboard/google/guybrush/Makefile.inc M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 3 files changed, 80 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
by Cliff Huang (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bora Guvendik, Lance Zhao, Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61352 to look at the new patch set (#6). Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... soc/intel/common/block/pcie/rtd3: Add PM methods to the device. Add L23 enter/exit, modPHY power gate, and source clock control methods. DL23: method for L2/L3 entry. L23D: method for L2/L3 exit. PSD0: method for modPHY power gate. SRCK: method for enabling/disable source clock. These optional methods are to be used in the device ACPI to construct flows with root port's power management functions. Test: Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 7: (15 comments) File src/soc/amd/cezanne/fch.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/002dd04a_77ffd724 PS7, Line 171: if (dxio_desc->engine_type != PCIE_ENGINE && dxio_desc->engine_type != UNUSED_ENGINE) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/45ae762e_036ead92 PS7, Line 186: printk(BIOS_WARNING, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/1c70e41d_c57e2dcc PS7, Line 187: "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/a916a6d1_19a30f0b PS7, Line 187: "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/f72517f2_d705e75c PS7, Line 188: dxio_desc->device_number, dxio_desc->function_number, i, gpp_req_index); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/1e4bd6b9_0148e7c2 PS7, Line 188: dxio_desc->device_number, dxio_desc->function_number, i, gpp_req_index); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/60f8b1f8_33ac2a3e PS7, Line 188: dxio_desc->device_number, dxio_desc->function_number, i, gpp_req_index); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/52529eae_9050b711 PS7, Line 192: /* Check for mismatches between disabled devices and SoC gpp_clk_config. */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/5cd34609_a859c0bb PS7, Line 193: if (!pci_device->enabled && cfg->gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/02e4e503_92595b33 PS7, Line 198: /* trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/769212dc_e3a837e0 PS7, Line 201: * by something other than a probe. trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/677ab328_7e41bb0e PS7, Line 203: printk(BIOS_WARNING, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/5ac9c34e_2fcb75a8 PS7, Line 205: dxio_desc->device_number, dxio_desc->function_number, gpp_req_index, i); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/6aaf385c_13cf9817 PS7, Line 209: dxio_desc->device_number, dxio_desc->function_number, gpp_req_index, i); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139821): https://review.coreboot.org/c/coreboot/+/61259/comment/50cba5b5_b0554357 PS7, Line 216: gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 01:17:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61259 to look at the new patch set (#7). Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... soc/amd/cezanne: Turn off gpp clock request for disabled devices The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled FIXED=b:202252869 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c --- M src/mainboard/google/guybrush/Makefile.inc M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 3 files changed, 75 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/fizz: update VBT for karma variant
by Matt DeVillier (Code Review) 03 Feb '22

03 Feb '22

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61579 ) Change subject: mb/google/fizz: update VBT for karma variant ...................................................................... mb/google/fizz: update VBT for karma variant Extracted from firmware image: bios-karma.ro-11343-22-0.rw-11343-22-0.bin Change-Id: Ic4165523a9114f748174c272ee206dfea80f4541 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/variants/karma/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/61579/1 diff --git a/src/mainboard/google/fizz/variants/karma/data.vbt b/src/mainboard/google/fizz/variants/karma/data.vbt index dbbf475..460c5ee 100644 --- a/src/mainboard/google/fizz/variants/karma/data.vbt +++ b/src/mainboard/google/fizz/variants/karma/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/61579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4165523a9114f748174c272ee206dfea80f4541 Gerrit-Change-Number: 61579 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
by Cliff Huang (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bora Guvendik, Lance Zhao, Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61352 ) Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/61352/comment/8d467f1d_b9656c65 PS5, Line 336: || pcie_rp > CONFIG_MAX_ROOT_PORTS > wasn't this part removed recently? […] I think so, will fix this. Good catch. -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 01:03:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [Test] [Do not Merge] alderlake: Update FSP ver to 2.3
by Anil Kumar K (Code Review) 03 Feb '22

03 Feb '22

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61577 ) Change subject: [Test] [Do not Merge] alderlake: Update FSP ver to 2.3 ...................................................................... [Test] [Do not Merge] alderlake: Update FSP ver to 2.3 Change-Id: Ibd9b502fc2106009bb0fc174d863fbfc1a7680ed --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/61577/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fa95088..5ceec0d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -56,7 +56,7 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_3 select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE @@ -103,7 +103,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC - select UDK_202005_BINDING + select UDK_202111_BINDING select DISPLAY_FSP_VERSION_INFO config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR -- To view, visit https://review.coreboot.org/c/coreboot/+/61577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd9b502fc2106009bb0fc174d863fbfc1a7680ed Gerrit-Change-Number: 61577 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2022