coreboot-gerrit February 2022

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Change in coreboot[master]: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61534 ) Change subject: soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI ...................................................................... soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It doesn't control if port 80s are written. This flag also doesn't currently control LPC init. The PSP is currently hard coded to remove any LPC init. BUG=b:215425753 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc 2 files changed, 5 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index f2fdc7f..620c650 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -342,13 +342,11 @@ help Disables the output of port80 post codes from PSP. -config PSP_POSTCODES_ON_ESPI - bool "Use eSPI bus for PSP post codes" - default y - depends on !PSP_DISABLE_POSTCODES +config PSP_INIT_ESPI + bool "Initialize eSPI in PSP Stage 2 Boot Loader" help - Select to send PSP port80 post codes on eSPI bus. - If not selected, PSP port80 codes will be sent on LPC bus. + Select to initialize the eSPI controller in the PSP Stage 2 Boot + Loader. config PSP_LOAD_MP2_FW bool diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5fda4b0..5708baa0 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -94,7 +94,7 @@ PSP_SOFTFUSE_BITS += 7 endif -ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) +ifeq ($(CONFIG_PSP_INIT_ESPI),y) PSP_SOFTFUSE_BITS += 15 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/61534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Gerrit-Change-Number: 61534 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: console: Add loglevel marker codes to stored consoles
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

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Change in coreboot[master]: console: Add ANSI escape sequences for highlighting
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Nico Huber, Patrick Georgi, Julius Werner, Kyösti Mälkki. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61307 ) Change subject: console: Add ANSI escape sequences for highlighting ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61307/comment/09655650_b55e94e5 PS3, Line 17: minicom picocom FTW! File src/commonlib/include/commonlib/loglevel.h: https://review.coreboot.org/c/coreboot/+/61307/comment/56505c39_b1f8dc01 PS3, Line 190: BIOS_LOG_ESCAPE_PATTERN Looks like this isn't used. If we did this in printk.c we could use `vtxprintf(wrap_putchar, BIOS_LOG_ESCAPE_PATTERN, args, NULL);` -- To view, visit https://review.coreboot.org/c/coreboot/+/61307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I868f4026918bc0e967c32e14bcf3ac05816415e8 Gerrit-Change-Number: 61307 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 23:19:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: console: Add loglevel prefix to interactive consoles
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Nico Huber, Patrick Georgi, Julius Werner, Kyösti Mälkki. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61306 ) Change subject: console: Add loglevel prefix to interactive consoles ...................................................................... Patch Set 3: (3 comments) File src/commonlib/include/commonlib/loglevel.h: https://review.coreboot.org/c/coreboot/+/61306/comment/74eef163_8b474aa1 PS3, Line 170: EMERG Maybe we can add color codes too! I use the following in my local workspace: https://review.coreboot.org/c/coreboot/+/61575 File src/console/console.c: https://review.coreboot.org/c/coreboot/+/61306/comment/b13fcdf0_dcb11c63 PS3, Line 27: line_start Let's move this function into printk.c (wrap_putchar). Then we don't need to pass around the `console_last_loglevel` via a global variable. I think it also makes sense to keep `console_tx_byte` simple. https://review.coreboot.org/c/coreboot/+/61306/comment/82a4e646_c173d656 PS3, Line 60: 0 nit: false -- To view, visit https://review.coreboot.org/c/coreboot/+/61306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Gerrit-Change-Number: 61306 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 23:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK: Enable color in console
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61575 ) Change subject: HACK: Enable color in console ...................................................................... HACK: Enable color in console Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic6639bf5202525b5fb32e57b9120450a33afed2b --- M src/console/printk.c 1 file changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/61575/1 diff --git a/src/console/printk.c b/src/console/printk.c index 1ed39cb..73c776e 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -68,10 +68,18 @@ { __cbmemc_tx_byte(byte); } +static void print_color(int msg_level, ...) +{ + va_list args; + + va_start(args, msg_level); + vtxprintf(wrap_putchar, "%s", args, NULL); + va_end(args); +} int vprintk(int msg_level, const char *fmt, va_list args) { - int i, log_this; + int i, log_this, color=0; if (CONFIG(SQUELCH_EARLY_SMP) && ENV_ROMSTAGE_OR_BEFORE && !boot_cpu()) return 0; @@ -87,7 +95,19 @@ if (log_this == CONSOLE_LOG_FAST) { i = vtxprintf(wrap_putchar_cbmemc, fmt, args, NULL); } else { + if (msg_level <= BIOS_ERR) { + print_color(msg_level, "\x1b[31;1m"); + color = 1; + } else if (msg_level == BIOS_WARNING) { + print_color(msg_level,"\x1b[31;33m"); + color = 1; + } + i = vtxprintf(wrap_putchar, fmt, args, NULL); + + if (color) + print_color(msg_level, "\x1b[31;0m"); // Reset + console_tx_flush(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6639bf5202525b5fb32e57b9120450a33afed2b Gerrit-Change-Number: 61575 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/graphics: Create Kconfig for shifting graphic memory base
by Wonkyu Kim (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Subrata Banik, Nico Huber, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 13 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 23:08:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add coreboot-configurator details to 4.15 release notes
by Sean Rhodes (Code Review) 03 Feb '22

03 Feb '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61574 ) Change subject: Documentation: Add coreboot-configurator details to 4.15 release notes ...................................................................... Documentation: Add coreboot-configurator details to 4.15 release notes Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I4666b9da29d85fdff215b83a985f7807d73beb77 --- M Documentation/releases/coreboot-4.16-relnotes.md 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/61574/1 diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md index 55317a4..52db9f1f 100644 --- a/Documentation/releases/coreboot-4.16-relnotes.md +++ b/Documentation/releases/coreboot-4.16-relnotes.md @@ -25,3 +25,10 @@ (working) and value of `1` will result in a (CS)ME state of `3` (disabled). For an example CMOS layout and more info, see [cse.c](../../src/soc/intel/common/block/cse/cse.c). + +### Add coreboot-configurator +A simple GUI to change CMOS settings in coreboot's CBFS, via the nvramtool utility. +Testing on Debian, Ubuntu and Manjaro with coreboot 4.14+, but should work with any +distribution or coreboot release that has an option table. For more info, please +check the [readme](util/coreboot-configurator/README.md). + -- To view, visit https://review.coreboot.org/c/coreboot/+/61574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4666b9da29d85fdff215b83a985f7807d73beb77 Gerrit-Change-Number: 61574 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add custom PLD fields to devicetree for brya variants
by Won Chung (Code Review) 03 Feb '22

03 Feb '22

Won Chung has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/61571 ) Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants ...................................................................... mb/google/brya: Add custom PLD fields to devicetree for brya variants BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung(a)google.com> Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 10 files changed, 476 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/61571/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 Gerrit-Change-Number: 61571 Gerrit-PatchSet: 2 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by Felix Held (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Mohan Viswanathan, Name of user not set #1004133, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 ) Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/61462/comment/10cb3c76_da7ada42 PS5, Line 128: return 0; not sure if this will do the right thing in the error case; the other implementation linked above might be better -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 5 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Name of user not set #1004133 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Mohan Viswanathan Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 22:57:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
by Raul Rangel (Code Review) 02 Feb '22

02 Feb '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61522 ) Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode ...................................................................... soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 3 files changed, 8 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 30f613a..41d318e 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -40,13 +40,3 @@ else svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION); } - - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) -{ - return 0; -} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 78f7126..12fccc3 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -140,3 +140,10 @@ SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); return retval; } + +uint32_t svc_write_postcode(uint32_t postcode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval); + return retval; +} diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index ff2144d..4cf9e70 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -51,6 +51,7 @@ #define SVC_SHA 0x69 #define SVC_CCP_DMA 0x6A #define SVC_SET_PLATFORM_BOOT_MODE 0x6C +#define SVC_WRITE_POSTCODE 0x6D struct mod_exp_params { char *pExponent; // Exponent address -- To view, visit https://review.coreboot.org/c/coreboot/+/61522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Gerrit-Change-Number: 61522 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2022