coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Inject CSE TS into timestamp_table
by Bora Guvendik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59507 to look at the new patch set (#11). Change subject: soc/intel/alderlake: Inject CSE TS into timestamp_table ...................................................................... soc/intel/alderlake: Inject CSE TS into timestamp_table Get boot performance timestamps from CSE and inject it into coreboot's timestamp table. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/telemetry.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59507/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/59507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Gerrit-Change-Number: 59507 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
by Kangheui Won (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61496 ) Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Gerrit-Change-Number: 61496 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 22:29:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
by Raul Rangel (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Kangheui Won, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61522 to look at the new patch set (#3). Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode ...................................................................... soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 3 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/61522/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Gerrit-Change-Number: 61522 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add memory config for nissa
by Kangheui Won (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Krishna P Bhat D, Usha P. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61439 ) Change subject: mb/google/brya: Add memory config for nissa ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d Gerrit-Change-Number: 61439 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 22:27:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/i2c: factor out common I2C pad configuration
by Felix Held (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61568 to look at the new patch set (#2). Change subject: soc/amd/*/i2c: factor out common I2C pad configuration ...................................................................... soc/amd/*/i2c: factor out common I2C pad configuration The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 --- M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/amd/majolica/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/i2c.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/common/block/i2c/Kconfig M src/soc/amd/common/block/i2c/Makefile.inc A src/soc/amd/common/block/i2c/i2c_pad_ctrl.c A src/soc/amd/common/block/i2c/i2c_pad_def.h M src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/chip.h M src/soc/amd/sabrina/i2c.c M src/soc/amd/sabrina/include/soc/southbridge.h 19 files changed, 134 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/61568/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Gerrit-Change-Number: 61568 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Inject CSE TS into timestamp_table
by Bora Guvendik (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59507 to look at the new patch set (#10). Change subject: soc/intel/alderlake: Inject CSE TS into timestamp_table ...................................................................... soc/intel/alderlake: Inject CSE TS into timestamp_table Get boot performance timestamps from CSE and inject it into coreboot's timestamp table. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/telemetry.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59507/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Gerrit-Change-Number: 59507 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Martin Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61550 to look at the new patch set (#4). Change subject: payloads/tianocore: Rework Makefile ...................................................................... payloads/tianocore: Rework Makefile Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This includes 3 new options: * TIANOCORE_BOOT_MANAGER_ESCAPE * TIANOCORE_HAVE_EFI_SHELL * TIANOCORE_FOLLOW_BGRT_SPEC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 120 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61550/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] soc/amd/sabrina/i2c: only call fch_i2c_pad_init for bus 3
by build bot (Jenkins) (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61570 ) Change subject: [WIP] soc/amd/sabrina/i2c: only call fch_i2c_pad_init for bus 3 ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/sabrina/i2c.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139796): https://review.coreboot.org/c/coreboot/+/61570/comment/3fc20a6c_bf364228 PS1, Line 45: if (bus <= 2) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/61570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 Gerrit-Change-Number: 61570 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Feb 2022 22:20:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp: check fsp image revision
by Felix Held (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Name of user not set #1003801, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61281 ) Change subject: soc/amd/common/fsp: check fsp image revision ...................................................................... Patch Set 12: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61281/comment/93437123_4b7080c5 PS2, Line 14: > Please mention what revision you define. the added example output from the serial console should have answered this, right? Commit Message: https://review.coreboot.org/c/coreboot/+/61281/comment/099dbb5e_e4732d88 PS11, Line 16: Picasso and Cezanne APUs. > Sabrina APU too Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Gerrit-Change-Number: 61281 Gerrit-PatchSet: 12 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Feb 2022 22:18:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Remove used build option
by Sean Rhodes (Code Review) 02 Feb '22

02 Feb '22

Attention is currently required from: Sean Rhodes, Martin Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61550 to look at the new patch set (#3). Change subject: payloads/tianocore: Remove used build option ...................................................................... payloads/tianocore: Remove used build option Remove -DPS2_KEYBOARD_ENABLE being passed to edk2 as it has no effect. The correct argument for PS2 Keyboard is: -D PS2_KEYBOARD_ENABLE=TRUE -D SIO_BUS_ENABLE=TRUE This is hard coded into uefipayload_202107. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 120 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61550/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2022