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Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
Patch Set 11:
(1 comment)
File src/soc/amd/common/block/psp/psb.c:
https://review.coreboot.org/c/coreboot/+/60968/comment/b6c57f96_c482d888
PS11, Line 133: static enum cb_err psb_get_hsti_status(uint32_t *status)
this basically does the same as https://review.coreboot.org/c/coreboot/+/61462/5/src/soc/amd/common/block/p… so it would be good to have a function for this in psp_gen2.c
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 5:
(4 comments)
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/61462/comment/b4f42f98_2ed87b9f
PS5, Line 34: select SOC_AMD_COMMON_BLOCK_PSP
this shouldn't be selected here. since this new option depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2, a dependency should be added here instead
File src/soc/amd/common/block/psp/psp.c:
https://review.coreboot.org/c/coreboot/+/61462/comment/0257bb9b_ef57821a
PS5, Line 80: BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY,
: psp_set_spl_fuse, NULL);
this should be moved to the psp_gen2 file which also avoids having to make this function visible outside of the psp_gen2 file
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/fc113136_45596763
PS5, Line 30: #define CORE_2_PSP_MSG_38_FUSE_SPL 0x00001000
at least for me this would be easier to read if it was in the BIT(x) or (1 << x) form
File src/soc/amd/common/block/psp/psp_gen2.c:
https://review.coreboot.org/c/coreboot/+/61462/comment/ecbd5c67_3742a2a5
PS5, Line 124: static u32 soc_read_c2p38(void)
commented on https://review.coreboot.org/c/coreboot/+/60968/11/src/soc/amd/common/block/… ; would be good if you could coordinate this and have one implementation here with a prototype in psp_def.h. a follow-up that does this would be fine too
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Change subject: Documentation/releases: Add 4.17 release notes template
......................................................................
Documentation/releases: Add 4.17 release notes template
Change-Id: Iffb95257fa99f3276f851507a0c9e4583c47bacc
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
---
A Documentation/releases/coreboot-4.17-relnotes.md
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/61573/1
diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md
new file mode 100644
index 0000000..a0d3650
--- /dev/null
+++ b/Documentation/releases/coreboot-4.17-relnotes.md
@@ -0,0 +1,19 @@
+Upcoming release - coreboot 4.17
+================================
+
+The 4.17 release is planned for May, 2022.
+
+We are continuing the quarterly release cadence in order to enable others to
+release quarterly on a fresher version of coreboot.
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+ before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here
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Change subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
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Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants
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Removed reviewer Tim Wawrzynczak.
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Change subject: spd/lp5: Generate initial SPDs for Sabrina SoC
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
I've added a new part in CB:61442 so you'll probably need to rebase (it should be submitted soon because that whole chain is ready to submit).
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Change subject: util/spd_tools/spd_gen: Add support for Sabrina SoC
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 5:
(3 comments)
File src/soc/amd/common/block/psp/psp.c:
PS4:
> this is psp gen 2 specific, so it needs to be moved to psp_gen2. […]
Done
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/099153dc_94cebf42
PS4, Line 21: #define MBOX_BIOS_CMD_SET_SPL_FUSE 0x2d
: #define MBOX_BIOS_CMD_QUERY_SPL_FUSE 0x47
> those two should be above MBOX_BIOS_CMD_ABORT so that those are in ascending order
Done
https://review.coreboot.org/c/coreboot/+/61462/comment/b78495b4_1d628c57
PS4, Line 29: 10998
> should this be 0x10998?
Confirmed with Avinash it is hex. Need to go back and look at the other C2P code that i used as reference.
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Change subject: soc/intel/graphics: Create Kconfig for shifting graphic memory base
......................................................................
Patch Set 13:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61389/comment/49076ea5_67b50ea3
PS11, Line 7: soc/intel/graphics: Create Kconfig for shifting graphic memory base
> > > Also, may be something like SOC_INTEL_GFX_GMADR_BEHIND_GTT could be your parent Kconfig which de […]
Done
https://review.coreboot.org/c/coreboot/+/61389/comment/af1ac7f5_03d0a2ef
PS11, Line 9: create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to
: shift graphic memory base if require.
> 72 characters wide please
Done
https://review.coreboot.org/c/coreboot/+/61389/comment/f796a017_86962f04
PS11, Line 10: require
> `required`
Done
File src/soc/intel/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/61389/comment/a5b6d1bb_d54858b1
PS11, Line 122: printk(BIOS_INFO, "gfx memory bar(0x18) = 0x%lx GFX_MEMBASE_OFFSET = 0x%x\n",
: memory_base, CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET);
> Can we also print out final memory_base? […]
This message is show 1 time during boot.
https://review.coreboot.org/c/coreboot/+/61389/comment/ce7139ba_e292f6b8
PS11, Line 129: memory_base = memory_base + CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET;
> I also think above memory_base checking for checking PCI config space 0x18 is programmed or not.
Done
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