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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61536 )
Change subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61536/comment/92e141de_63a8a5db
PS6, Line 8:
> Please describe the problem.
Done
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Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61536
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
......................................................................
soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.
The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state
BUG=b:193287279
TEST=Built coreboot on Gimble and tested type A pen drive detects as
super speed device
Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/include/soc/usb.h
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/61536/7
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60995 )
Change subject: mb/google/brya: Add GPIO table for nissa
......................................................................
Patch Set 9: Code-Review+2
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Change subject: mb/amd/chausie/devicetree: update I2C RX levels to match board design
......................................................................
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Change subject: soc/amd/*/i2c: factor out common I2C pad configuration
......................................................................
Patch Set 1: Code-Review+2
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Hello Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro
......................................................................
soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b
---
M src/soc/amd/cezanne/i2c.c
M src/soc/amd/cezanne/include/soc/southbridge.h
M src/soc/amd/picasso/i2c.c
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/sabrina/i2c.c
M src/soc/amd/sabrina/include/soc/southbridge.h
6 files changed, 9 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/61567/2
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Change subject: soc/amd/*/i2c: introduce and use MISC_I2CX_PAD_CTRL(bus) macro
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/*/i2c: drop unused mainboard_i2c_override
......................................................................
Patch Set 1: Code-Review+2
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