coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0
by Varshit B Pandya (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61595 to look at the new patch set (#2). Change subject: mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0 ...................................................................... mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0 This Kconfig will generate ACPI entries related to DDRRFIM. Which will be used by wifi driver. BUG=b:201724512 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ia90f8aa4ab18cf4292bb89d152fb6acffc5c52f6 --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61595/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia90f8aa4ab18cf4292bb89d152fb6acffc5c52f6 Gerrit-Change-Number: 61595 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/driver/wifi: Add _DSM method for DDRRFIM
by build bot (Jenkins) (Code Review) 03 Feb '22

03 Feb '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61594 ) Change subject: src/driver/wifi: Add _DSM method for DDRRFIM ...................................................................... Patch Set 1: (2 comments) File src/drivers/wifi/generic/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139877): https://review.coreboot.org/c/coreboot/+/61594/comment/3e818470_df91afae PS1, Line 489: union wifi_sar_limits sar_limits = {{NULL, NULL, NULL, NULL, NULL}}; space required after that close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139877): https://review.coreboot.org/c/coreboot/+/61594/comment/83ec7f96_2a093784 PS1, Line 511: if (sar_limits.dsm != NULL) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/61594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08dce3db5f9f41195e88543f5dde1578572dbd27 Gerrit-Change-Number: 61594 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Feb 2022 15:03:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0
by Varshit B Pandya (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Tim Wawrzynczak. Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61595 ) Change subject: mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0 ...................................................................... mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0 This Kconfig will generate ACPI entries related to DDRRFIM. Which will be used by wifi driver. BUG=b:201724512 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ia90f8aa4ab18cf4292bb89d152fb6acffc5c52f6 --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61595/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 0a3b1d9..e227d41 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -36,6 +36,7 @@ select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG + select USE_DDR_RFIM_DSM config BOARD_GOOGLE_BRYA4ES bool "-> Brya4ES" -- To view, visit https://review.coreboot.org/c/coreboot/+/61595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia90f8aa4ab18cf4292bb89d152fb6acffc5c52f6 Gerrit-Change-Number: 61595 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/driver/wifi: Add _DSM method for DDRRFIM
by Varshit B Pandya (Code Review) 03 Feb '22

03 Feb '22

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61594 ) Change subject: src/driver/wifi: Add _DSM method for DDRRFIM ...................................................................... src/driver/wifi: Add _DSM method for DDRRFIM coreboot need to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This patch adds _DSM method for that. Add support for following 2 function in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable BUG=b:201724512 TEST=Build, boot brya0 and dump SSDT entries Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x09 // . }) } If ((Local1 == One)){} If ((Local1 == 0x02)){} If ((Local1 == 0x03)) { Return (Zero) } Return (Buffer (One) { 0x00 // . }) } Return (Buffer (One) { 0x00 // . }) } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I08dce3db5f9f41195e88543f5dde1578572dbd27 --- M src/drivers/wifi/generic/acpi.c 1 file changed, 62 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61594/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 3cc1c63..70e6a1e 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <sar.h> +#include <soc/soc_chip.h> #include <stdlib.h> #include <wrdd.h> @@ -15,6 +16,9 @@ /* WIFI Domain type */ #define DOMAIN_TYPE_WIFI 0x7 +/* Maximum number DSM UUID bifurcations in _DSM */ +#define MAX_DSM_FUNCS 2 + /* * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0' * The above representation returns unique and consistent name every time @@ -26,6 +30,9 @@ /* Unique ID for the WIFI _DSM */ #define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" +/* Unique ID for CnviDdrRfim entry in WIFI _DSM */ +#define ACPI_DSM_RFIM_WIFI_UUID "7266172C-220B-4B29-814F-75E4DD26B5FD" + __weak int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { return -1; @@ -142,6 +149,13 @@ acpigen_write_return_integer(dsm_config->unii_4); } +static void wifi_dsm_ddrrfim_func3_cb(void *ptr) +{ + config_t *config = config_of_soc(); + + acpigen_write_return_integer(config->CnviDdrRfim); +} + static void (*wifi_dsm_callbacks[])(void *) = { NULL, /* Function 0 */ wifi_dsm_srd_active_channels, /* Function 1 */ @@ -153,6 +167,17 @@ wifi_dsm_unii4_control_enable, /* Function 7 */ }; +/* + * The current DSM2 table is only exporting one function (function 3), some more + * functions are reserved so marking them NULL. +*/ +static void (*wifi_dsm2_callbacks[])(void *) = { + NULL, /* Function 0 */ + NULL, /* Function 1 */ + NULL, /* Function 2 */ + wifi_dsm_ddrrfim_func3_cb, /* Function 3 */ +}; + void wifi_emit_dsm(struct dsm_profile *dsm) { int i; @@ -459,9 +484,9 @@ acpigen_write_package_end(); } -static void emit_sar_acpi_structures(const struct device *dev) +static void emit_sar_acpi_structures(const struct device *dev, struct dsm_profile *dsm) { - union wifi_sar_limits sar_limits; + union wifi_sar_limits sar_limits = {{NULL, NULL, NULL, NULL, NULL}}; /* * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR @@ -481,7 +506,11 @@ sar_emit_wgds(sar_limits.wgds); sar_emit_ppag(sar_limits.ppag); sar_emit_wtas(sar_limits.wtas); - wifi_emit_dsm(sar_limits.dsm); + + /* copy the dsm data to be later used for creating _DSM function */ + if (sar_limits.dsm != NULL) { + memcpy(dsm, &sar_limits.dsm, sizeof(struct dsm_profile)); + } free(sar_limits.sar); } @@ -533,9 +562,37 @@ acpigen_pop_len(); } + struct dsm_uuid dsm_ids[MAX_DSM_FUNCS]; + /* We will need a copy dsm data to be used later for creating _DSM function */ + struct dsm_profile dsm = {0}; + uint8_t dsm_count = 0; + /* Fill Wifi sar related ACPI structures */ - if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(dev); + if (CONFIG(USE_SAR)) { + emit_sar_acpi_structures(dev, &dsm); + + if (dsm.supported_functions != 0) { + for (int i = 1; i < ARRAY_SIZE(wifi_dsm_callbacks); i++) + if (!(dsm.supported_functions & (1 << i))) + wifi_dsm_callbacks[i] = NULL; + + dsm_ids[dsm_count].uuid = ACPI_DSM_OEM_WIFI_UUID; + dsm_ids[dsm_count].callbacks = &wifi_dsm_callbacks[0]; + dsm_ids[dsm_count].count = ARRAY_SIZE(wifi_dsm_callbacks); + dsm_ids[dsm_count].arg = NULL; + dsm_count++; + } + } + + if (CONFIG(USE_DDR_RFIM_DSM)) { + dsm_ids[dsm_count].uuid = ACPI_DSM_RFIM_WIFI_UUID; + dsm_ids[dsm_count].callbacks = &wifi_dsm2_callbacks[0]; + dsm_ids[dsm_count].count = ARRAY_SIZE(wifi_dsm2_callbacks); + dsm_ids[dsm_count].arg = NULL; + dsm_count++; + } + + acpigen_write_dsm_uuid_arr(dsm_ids, dsm_count); acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08dce3db5f9f41195e88543f5dde1578572dbd27 Gerrit-Change-Number: 61594 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/drivers/wifi: Adding Kconfig for DDRRFIM
by Varshit B Pandya (Code Review) 03 Feb '22

03 Feb '22

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61593 ) Change subject: src/drivers/wifi: Adding Kconfig for DDRRFIM ...................................................................... src/drivers/wifi: Adding Kconfig for DDRRFIM Add USE_DDR_RFIM_DSM in driver Kconfig This will generate ACPI entries required by the wifi driver BUG=b:201724512 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ica6fd991b714add54feb898723bfbfeab63a2e0c --- M src/drivers/wifi/generic/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/61593/1 diff --git a/src/drivers/wifi/generic/Kconfig b/src/drivers/wifi/generic/Kconfig index 1d0e19f..e813140 100644 --- a/src/drivers/wifi/generic/Kconfig +++ b/src/drivers/wifi/generic/Kconfig @@ -49,4 +49,10 @@ help There can be up to 3 optional SAR table sets. +config USE_DDR_RFIM_DSM + bool + default n + help + Enable it when mainboard is using DDRRFIM + endif # DRIVERS_WIFI_GENERIC -- To view, visit https://review.coreboot.org/c/coreboot/+/61593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica6fd991b714add54feb898723bfbfeab63a2e0c Gerrit-Change-Number: 61593 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Implement variant_cros_gpios() for nissa baseboard
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61497 ) Change subject: mb/google/brya: Implement variant_cros_gpios() for nissa baseboard ...................................................................... mb/google/brya: Implement variant_cros_gpios() for nissa baseboard BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ib49164cf51965228c65c6566b0711ae690b6cb50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61497 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index 9d4f5a6..8a3ea0e 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -429,7 +429,8 @@ } static const struct cros_gpio cros_gpios[] = { - /* TODO */ + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/61497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49164cf51965228c65c6566b0711ae690b6cb50 Gerrit-Change-Number: 61497 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61496 ) Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 ...................................................................... mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 In the nivviks and nereid pre-proto builds, the memory straps used don't match those generated by spd_tools. Each pre-proto build only supports a single memory part, and each of these parts should have ID 0 (see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code the memory IDs to 0 instead of reading them from the memory strap pins. From P1 onwards, the memory straps will be assigned based on the IDs generated by spd_tools. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61496 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/variants/nereid/Makefile.inc A src/mainboard/google/brya/variants/nereid/memory.c M src/mainboard/google/brya/variants/nivviks/Makefile.inc A src/mainboard/google/brya/variants/nivviks/memory.c 4 files changed, 64 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nereid/Makefile.inc b/src/mainboard/google/brya/variants/nereid/Makefile.inc index 58c4d79..defb592 100644 --- a/src/mainboard/google/brya/variants/nereid/Makefile.inc +++ b/src/mainboard/google/brya/variants/nereid/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c + romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nereid/memory.c b/src/mainboard/google/brya/variants/nereid/memory.c new file mode 100644 index 0000000..0453cf1 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> + +int variant_memory_sku(void) +{ + /* + * The memory straps in the P0 build don't match those generated by + * spd_tools, so override the memory ID to 0. + */ + if (board_id() == 0) + return 0; + + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/brya/variants/nivviks/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/Makefile.inc index 58c4d79..defb592 100644 --- a/src/mainboard/google/brya/variants/nivviks/Makefile.inc +++ b/src/mainboard/google/brya/variants/nivviks/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c + romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nivviks/memory.c b/src/mainboard/google/brya/variants/nivviks/memory.c new file mode 100644 index 0000000..0453cf1 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> + +int variant_memory_sku(void) +{ + /* + * The memory straps in the P0 build don't match those generated by + * spd_tools, so override the memory ID to 0. + */ + if (board_id() == 0) + return 0; + + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Gerrit-Change-Number: 61496 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add SPD configs for nivviks and nereid
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61443 ) Change subject: mb/google/brya: Add SPD configs for nivviks and nereid ...................................................................... mb/google/brya: Add SPD configs for nivviks and nereid Add a mem_parts_used.txt for each of nivviks and nereid, containing the memory parts used in their pre-proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. nivviks: Micron MT62F1G32D4DR-031 WT:B nereid: Samsung K3LKBKB0BM-MGCP BUG=b:197479026 TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom contains an spd.bin. Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61443 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/nereid/memory/Makefile.inc A src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc A src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt 7 files changed, 53 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 45e55bf..c0b8a34 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -59,6 +59,7 @@ def_bool n select BOARD_GOOGLE_BRYA_COMMON select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc new file mode 100644 index 0000000..f39c69a --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt new file mode 100644 index 0000000..cce733c --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +K3LKBKB0BM-MGCP 0 (0000) diff --git a/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt new file mode 100644 index 0000000..c092a5f --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc new file mode 100644 index 0000000..db35a4d --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt new file mode 100644 index 0000000..1ad0e36 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt new file mode 100644 index 0000000..9c853bd --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67 Gerrit-Change-Number: 61443 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Fill in ec.h for nissa baseboard
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61440 ) Change subject: mb/google/brya: Fill in ec.h for nissa baseboard ...................................................................... mb/google/brya: Fill in ec.h for nissa baseboard BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: I322a94569d8a63e8c0da68a8feb394ade4ce7999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61440 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h 1 file changed, 76 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h index a2210c6..fa5af03 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h @@ -7,12 +7,81 @@ #include <ec/google/chromeec/ec_commands.h> #include <baseboard/gpio.h> -/* TODO: Set the correct values */ -#define MAINBOARD_EC_SCI_EVENTS 0 -#define MAINBOARD_EC_SMI_EVENTS 0 -#define MAINBOARD_EC_S5_WAKE_EVENTS 0 -#define MAINBOARD_EC_S3_WAKE_EVENTS 0 -#define MAINBOARD_EC_S0IX_WAKE_EVENTS 0 -#define MAINBOARD_EC_LOG_EVENTS 0 +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. AC Connect/Disconnect + * 4. Key press + * 5. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable Keyboard Backlight */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp support */ #endif /* __BASEBOARD_EC_H__ */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I322a94569d8a63e8c0da68a8feb394ade4ce7999 Gerrit-Change-Number: 61440 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add memory config for nissa
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61439 ) Change subject: mb/google/brya: Add memory config for nissa ...................................................................... mb/google/brya: Add memory config for nissa Fill in the memory config based on the the schematic and doc #573387. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61439 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/nissa/memory.c 1 file changed, 90 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/memory.c b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c index 420b366..d4f9a0b 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c @@ -3,20 +3,106 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 36, 35, 35, 35 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; const struct mb_cfg *__weak variant_memory_params(void) { - /* TODO */ - return NULL; + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } bool __weak variant_is_half_populated(void) { - /* TODO */ + /* ADL-N only has a single memory channel. */ return false; } void __weak variant_get_spd_info(struct mem_spd *spd_info) { - /* TODO */ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d Gerrit-Change-Number: 61439 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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