Attention is currently required from: Tim Wawrzynczak.
Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61595 )
Change subject: mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0
......................................................................
mb/google/brya/var/brya0: Add USE_DDR_RFIM_DSM Kconfig for brya0
This Kconfig will generate ACPI entries related to DDRRFIM.
Which will be used by wifi driver.
BUG=b:201724512
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: Ia90f8aa4ab18cf4292bb89d152fb6acffc5c52f6
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61595/1
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 0a3b1d9..e227d41 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -36,6 +36,7 @@
select HAVE_WWAN_POWER_SEQUENCE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CRASHLOG
+ select USE_DDR_RFIM_DSM
config BOARD_GOOGLE_BRYA4ES
bool "-> Brya4ES"
--
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Gerrit-Change-Id: Ia90f8aa4ab18cf4292bb89d152fb6acffc5c52f6
Gerrit-Change-Number: 61595
Gerrit-PatchSet: 1
Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Gerrit-MessageType: newchange
Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61593 )
Change subject: src/drivers/wifi: Adding Kconfig for DDRRFIM
......................................................................
src/drivers/wifi: Adding Kconfig for DDRRFIM
Add USE_DDR_RFIM_DSM in driver Kconfig
This will generate ACPI entries required by the wifi driver
BUG=b:201724512
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: Ica6fd991b714add54feb898723bfbfeab63a2e0c
---
M src/drivers/wifi/generic/Kconfig
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/61593/1
diff --git a/src/drivers/wifi/generic/Kconfig b/src/drivers/wifi/generic/Kconfig
index 1d0e19f..e813140 100644
--- a/src/drivers/wifi/generic/Kconfig
+++ b/src/drivers/wifi/generic/Kconfig
@@ -49,4 +49,10 @@
help
There can be up to 3 optional SAR table sets.
+config USE_DDR_RFIM_DSM
+ bool
+ default n
+ help
+ Enable it when mainboard is using DDRRFIM
+
endif # DRIVERS_WIFI_GENERIC
--
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Gerrit-Change-Number: 61593
Gerrit-PatchSet: 1
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61496 )
Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
......................................................................
mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
In the nivviks and nereid pre-proto builds, the memory straps used
don't match those generated by spd_tools. Each pre-proto build only
supports a single memory part, and each of these parts should have ID 0
(see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code
the memory IDs to 0 instead of reading them from the memory strap pins.
From P1 onwards, the memory straps will be assigned based on the IDs
generated by spd_tools.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61496
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
---
M src/mainboard/google/brya/variants/nereid/Makefile.inc
A src/mainboard/google/brya/variants/nereid/memory.c
M src/mainboard/google/brya/variants/nivviks/Makefile.inc
A src/mainboard/google/brya/variants/nivviks/memory.c
4 files changed, 64 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kangheui Won: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/nereid/Makefile.inc b/src/mainboard/google/brya/variants/nereid/Makefile.inc
index 58c4d79..defb592 100644
--- a/src/mainboard/google/brya/variants/nereid/Makefile.inc
+++ b/src/mainboard/google/brya/variants/nereid/Makefile.inc
@@ -1,4 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
+
romstage-y += gpio.c
+romstage-y += memory.c
+
ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/nereid/memory.c b/src/mainboard/google/brya/variants/nereid/memory.c
new file mode 100644
index 0000000..0453cf1
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+
+int variant_memory_sku(void)
+{
+ /*
+ * The memory straps in the P0 build don't match those generated by
+ * spd_tools, so override the memory ID to 0.
+ */
+ if (board_id() == 0)
+ return 0;
+
+ /*
+ * Memory configuration board straps
+ * GPIO_MEM_CONFIG_0 GPP_E1
+ * GPIO_MEM_CONFIG_1 GPP_E2
+ * GPIO_MEM_CONFIG_2 GPP_E3
+ */
+ gpio_t spd_gpios[] = {
+ GPP_E1,
+ GPP_E2,
+ GPP_E3,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
diff --git a/src/mainboard/google/brya/variants/nivviks/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/Makefile.inc
index 58c4d79..defb592 100644
--- a/src/mainboard/google/brya/variants/nivviks/Makefile.inc
+++ b/src/mainboard/google/brya/variants/nivviks/Makefile.inc
@@ -1,4 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
+
romstage-y += gpio.c
+romstage-y += memory.c
+
ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/nivviks/memory.c b/src/mainboard/google/brya/variants/nivviks/memory.c
new file mode 100644
index 0000000..0453cf1
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+
+int variant_memory_sku(void)
+{
+ /*
+ * The memory straps in the P0 build don't match those generated by
+ * spd_tools, so override the memory ID to 0.
+ */
+ if (board_id() == 0)
+ return 0;
+
+ /*
+ * Memory configuration board straps
+ * GPIO_MEM_CONFIG_0 GPP_E1
+ * GPIO_MEM_CONFIG_1 GPP_E2
+ * GPIO_MEM_CONFIG_2 GPP_E3
+ */
+ gpio_t spd_gpios[] = {
+ GPP_E1,
+ GPP_E2,
+ GPP_E3,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d
Gerrit-Change-Number: 61496
Gerrit-PatchSet: 4
Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org>
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Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61443 )
Change subject: mb/google/brya: Add SPD configs for nivviks and nereid
......................................................................
mb/google/brya: Add SPD configs for nivviks and nereid
Add a mem_parts_used.txt for each of nivviks and nereid, containing the
memory parts used in their pre-proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.
nivviks:
Micron MT62F1G32D4DR-031 WT:B
nereid:
Samsung K3LKBKB0BM-MGCP
BUG=b:197479026
TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom
contains an spd.bin.
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61443
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/nereid/memory/Makefile.inc
A src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
A src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
7 files changed, 53 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kangheui Won: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 45e55bf..c0b8a34 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -59,6 +59,7 @@
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+ select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_N
select SYSTEM_TYPE_LAPTOP
diff --git a/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc
new file mode 100644
index 0000000..f39c69a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = K3LKBKB0BM-MGCP
diff --git a/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt
new file mode 100644
index 0000000..cce733c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+K3LKBKB0BM-MGCP 0 (0000)
diff --git a/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
new file mode 100644
index 0000000..c092a5f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+K3LKBKB0BM-MGCP
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
new file mode 100644
index 0000000..db35a4d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
new file mode 100644
index 0000000..1ad0e36
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+MT62F1G32D4DR-031 WT:B 0 (0000)
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9c853bd
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+MT62F1G32D4DR-031 WT:B
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Gerrit-Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67
Gerrit-Change-Number: 61443
Gerrit-PatchSet: 3
Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61348 )
Change subject: mb/google/brya: Fill in gpio.h for nissa baseboard
......................................................................
mb/google/brya: Fill in gpio.h for nissa baseboard
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: I7ec4b9368e0a63c0c0c9a92c8367a89d57f10d51
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61348
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
1 file changed, 10 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
Kangheui Won: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
index 9ca9ee7..068aaa4 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
@@ -6,10 +6,15 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
-/* TODO: Set the correct values */
-#define EC_SCI_GPI 0
-#define GPIO_PCH_WP 0
-#define GPIO_EC_IN_RW 0
-#define GPIO_SLP_S0_GATE 0
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
+#define GPE_EC_WAKE GPE0_DW2_17
+/* WP signal to PCH */
+#define GPIO_PCH_WP GPP_E12
+/* EC in RW or RO */
+#define GPIO_EC_IN_RW GPP_F18
+/* GPIO IRQ for tight timestamps */
+#define EC_SYNC_IRQ GPD2_IRQ
#endif /* __BASEBOARD_GPIO_H__ */
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Gerrit-Branch: master
Gerrit-Change-Id: I7ec4b9368e0a63c0c0c9a92c8367a89d57f10d51
Gerrit-Change-Number: 61348
Gerrit-PatchSet: 6
Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org>
Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61347 )
Change subject: mb/google/brya: Add Kconfig for SLP_S0_GATE
......................................................................
mb/google/brya: Add Kconfig for SLP_S0_GATE
Nissa doesn't have a SLP_S0_GATE signal, so we shouldn't generate the
related ACPI code. Therefore, move this behind a Kconfig which is
currently selected by the brya and brask baseboards.
BUG=b:197479026
TEST=Build brya0, check that there's no change to the generated dsdt.asl
Change-Id: I5a73c6794f6d3977cbff47aeff571154e41944cc
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61347
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/mainboard.asl
2 files changed, 7 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 34d9cba..45e55bf 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -39,6 +39,7 @@
config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
+ select HAVE_SLP_S0_GATE
select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
select SOC_INTEL_ALDERLAKE_PCH_P
select SYSTEM_TYPE_LAPTOP
@@ -47,6 +48,7 @@
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
+ select HAVE_SLP_S0_GATE
select MEMORY_SODIMM
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
@@ -227,4 +229,7 @@
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select HAVE_SPD_IN_CBFS
+config HAVE_SLP_S0_GATE
+ def_bool n
+
endif # BOARD_GOOGLE_BRYA_COMMON
diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl
index c60db30..8ca694d 100644
--- a/src/mainboard/google/brya/mainboard.asl
+++ b/src/mainboard/google/brya/mainboard.asl
@@ -2,6 +2,7 @@
#include <baseboard/gpio.h>
+#if CONFIG(HAVE_SLP_S0_GATE)
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
@@ -22,3 +23,4 @@
\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
}
}
+#endif
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Gerrit-Project: coreboot
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