coreboot-gerrit December 2022

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[M] Change in coreboot[master]: amdfwtool: Add the new entry type for new family glinda & morgana
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Martin Roth. Hello build bot (Jenkins), Jason Glenesk, Martin L Roth, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69045 to look at the new patch set (#10). Change subject: amdfwtool: Add the new entry type for new family glinda & morgana ...................................................................... amdfwtool: Add the new entry type for new family glinda & morgana Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 127 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/69045/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Gerrit-Change-Number: 69045 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: intelp2m: Update cli options
by Maxim Polyakov (Code Review) 04 Dec '22

04 Dec '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70310 to look at the new patch set (#2). Change subject: intelp2m: Update cli options ...................................................................... intelp2m: Update cli options Use the new options format: basic functions: -file <path> path to the inteltool log file -out <path> path to the generated file -platform <type> set the PCH platform type <sunrise> enter ? to show details generation of long composite macros with bit field definitions: -fields <type> generate a long macro consisting of bitfield macros enter ? to show details control flags: -exclude exclude fields that should be ignored to gen macro -unchecked disable automatic checking of macro fields before gen generate additional information: -i add function to the comments -ii add DW0/DW1 register value to the comments -iii add ignored bitfields to the comments -iiii add target PAD_CFG() macro to the comments Use the following bash command: $ complete `-C `pwd`/intelp2m ./intelp2m to allow automatic completion of arguments Change-Id: I08ff379b99b018b1099aa5d70fea47026bc84045 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/cli/completion.go A util/intelp2m/cli/options.go M util/intelp2m/config/p2m/config.go M util/intelp2m/main.go 4 files changed, 202 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/70310/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08ff379b99b018b1099aa5d70fea47026bc84045 Gerrit-Change-Number: 70310 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: src/ec/intel: Create common code for board_id implementation
by Harsha B R (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70227 ) Change subject: src/ec/intel: Create common code for board_id implementation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Ping! -- To view, visit https://review.coreboot.org/c/coreboot/+/70227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Gerrit-Change-Number: 70227 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Sun, 04 Dec 2022 11:02:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by build bot (Jenkins) (Code Review) 04 Dec '22

04 Dec '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64873 ) Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches ...................................................................... Patch Set 4: (6 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165188): https://review.coreboot.org/c/coreboot/+/64873/comment/2368b8c9_39745678 PS4, Line 20: Please share your feedback/suggestions and tell about other useful patches, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165188): https://review.coreboot.org/c/coreboot/+/64873/comment/85c9a94a_89bcd038 PS4, Line 23: 1) "board-specific": Lenovo G505S discrete GPU support, custom SeaBIOS options, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165188): https://review.coreboot.org/c/coreboot/+/64873/comment/28493291_97126604 PS4, Line 24: example configs for G505S / AM1I-A / A88XM-E and known good AtomBIOS ROMs, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165188): https://review.coreboot.org/c/coreboot/+/64873/comment/d20d3c28_d7698e74 PS4, Line 25: and also good IRQ routing for AMD Lenovo G505S, ASUS A88XM-E and AM1I-A boards. Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165188): https://review.coreboot.org/c/coreboot/+/64873/comment/24eee12e_fef6186f PS4, Line 31: Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information. Possible unwrapped commit description (prefer a maximum 72 chars per line) File csb_patcher.sh: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165188): https://review.coreboot.org/c/coreboot/+/64873/comment/4eea6f53_366ab178 PS4, Line 752: printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n" 'README' may be misspelled - perhaps 'README'? -- To view, visit https://review.coreboot.org/c/coreboot/+/64873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2 Gerrit-Change-Number: 64873 Gerrit-PatchSet: 4 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 04 Dec 2022 08:23:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review) 04 Dec '22

04 Dec '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64873 to look at the new patch set (#4). Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches ...................................................................... csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches Conveniently and securely gets, checks SHA256 and installs some of my patches from this page - https://review.coreboot.org/q/status:open+banon - and also gets a collection of useful floppy-based operating systems. Sometimes it takes quite a long time to get a patch merged, while the people might need it today! - and this script could be really helpful. It asks a [Y/N] question for every addition, and since there are some "universal" patches as well as great floppies, you may still want to run this script - even if your board is not Lenovo G505S or not AMD. Please share your feedback/suggestions and tell about other useful patches, preferably the "universal" ones - i.e. SeaBIOS. Currently included: 1) "board-specific": Lenovo G505S discrete GPU support, custom SeaBIOS options, example configs for G505S / AM1I-A / A88XM-E and known good AtomBIOS ROMs, and also good IRQ routing for AMD Lenovo G505S, ASUS A88XM-E and AM1I-A boards. 2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies, smbios_mptable_768; and also a floppies collection: KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird. Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information. Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2 --- A csb_patcher.sh 1 file changed, 960 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/64873/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2 Gerrit-Change-Number: 64873 Gerrit-PatchSet: 4 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/sandybridge: Use write32p()
by Elyes Haouas (Code Review) 04 Dec '22

04 Dec '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70293 ) Change subject: nb/intel/sandybridge: Use write32p() ...................................................................... nb/intel/sandybridge: Use write32p() Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/raminit_common.c 2 files changed, 19 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/70293/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 7acc5af..e3525135 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -23,14 +23,14 @@ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1); /* Lock policies */ - write32((void *)(GFXVT_BASE + 0xff0), 0x80000000); + write32p(GFXVT_BASE + 0xff0, 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { - write32((void *)(VTVC0_BASE + 0xff0), 0x20000000); - write32((void *)(VTVC0_BASE + 0xff0), 0xa0000000); + write32p(VTVC0_BASE + 0xff0, 0x20000000); + write32p(VTVC0_BASE + 0xff0, 0xa0000000); } else { - write32((void *)(VTVC0_BASE + 0xff0), 0x80000000); + write32p(VTVC0_BASE + 0xff0, 0x80000000); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4e95815..b3f913e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1513,7 +1513,7 @@ for (j = 0; j < 16; j++) { addr = 0x04000000 + channel_offset + 4 * j; - write32((void *)addr, j & 2 ? b : a); + write32p(addr, j & 2 ? b : a); } sfence(); @@ -1538,11 +1538,11 @@ for (j = 0; j < 16; j++) { addr = 0x04000000 + channel_offset + j * 4; - write32((void *)addr, 0xffffffff); + write32p(addr, 0xffffffff); } for (j = 0; j < 16; j++) { addr = 0x04000000 + channel_offset + channel_step + j * 4; - write32((void *)addr, 0); + write32p(addr, 0); } sfence(); @@ -1948,7 +1948,7 @@ val = ~val; addr = (1 << 26) + offset + i * step + j * 4; - write32((void *)addr, val); + write32p(addr, val); } } } else { @@ -1956,7 +1956,7 @@ for (j = 0; j < 16; j++) { const u32 val = pattern[i][j]; addr = (1 << 26) + offset + i * step + j * 4; - write32((void *)addr, val); + write32p(addr, val); } } sfence(); -- To view, visit https://review.coreboot.org/c/coreboot/+/70293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520 Gerrit-Change-Number: 70293 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel/bd82x6x: Use {read,write}32p
by Elyes Haouas (Code Review) 04 Dec '22

04 Dec '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70292 ) Change subject: sb/intel/bd82x6x: Use {read,write}32p ...................................................................... sb/intel/bd82x6x: Use {read,write}32p While on it, sort includes. Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c 2 files changed, 29 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/70292/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 28337f6..bf03b1a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -1,20 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <arch/io.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <commonlib/region.h> -#include <device/pci_def.h> -#include <cpu/x86/smm.h> +#include <console/console.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <cpu/x86/smm.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <soc/nvs.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/gpio.h> -#include <cpu/intel/model_206ax/model_206ax.h> -#include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/finalize.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmutil.h> +#include <types.h> #include "pch.h" @@ -168,7 +169,7 @@ /* Steps 3 to 6: If USB3 PORTSC current connect status (bit 0) is set, do IOBP magic */ for (unsigned int port = 0; port < 4; port++) { - if (read32((void *)(xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0)) + if (read32p((xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0)) pch_iobp_update(0xec000082 + 0x100 * port, ~0, 3 << 2); } diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 3661aba..1cb260a 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -2,12 +2,13 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "pch.h" -#include <device/pci_ehci.h> #include <device/mmio.h> +#include <device/pci_ehci.h> +#include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci.h> + +#include "pch.h" static void usb_ehci_init(struct device *dev) { @@ -46,8 +47,8 @@ res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ - reg32 = read32((void *)(uintptr_t)(res->base + 4)); - write32((void *)(uintptr_t)(res->base + 4), + reg32 = read32p((uintptr_t)(res->base + 4)); + write32p((uintptr_t)(res->base + 4), (reg32 & 0xfff00000) | 3); } -- To view, visit https://review.coreboot.org/c/coreboot/+/70292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f Gerrit-Change-Number: 70292 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: /: Include <device/mmio.h> instead of <arch/mmio.h>
by Elyes Haouas (Code Review) 04 Dec '22

04 Dec '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70291 ) Change subject: /: Include <device/mmio.h> instead of <arch/mmio.h> ...................................................................... /: Include <device/mmio.h> instead of <arch/mmio.h> <device/mmio.h>` chain-include `<arch/mmio.h>. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/xhci.c M src/drivers/emulation/qemu/bochs.c M src/drivers/intel/ptt/ptt.c M src/drivers/siemens/nc_fpga/nc_fpga_early.c M src/include/cpu/x86/lapic.h M src/mainboard/google/dedede/fw_config.c M src/mainboard/google/dedede/variants/bugzzy/ramstage.c M src/mainboard/protectli/vault_bsw/mainboard.c M src/mainboard/scaleway/tagada/hsio.c M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c M src/northbridge/intel/x4x/bootblock.c M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/intel/txt/romstage.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_efs.c M src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/picasso/agesa_acpi.c M src/soc/intel/alderlake/bootblock/update_descriptor.c M src/southbridge/intel/lynxpoint/uart_init.c M util/inteltool/inteltool.h 23 files changed, 35 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/70291/1 diff --git a/src/device/xhci.c b/src/device/xhci.c index 4523b56..0e74993 100644 --- a/src/device/xhci.c +++ b/src/device/xhci.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <device/pci_def.h> #include <device/xhci.h> diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index d3b9007..b78773f 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -2,7 +2,7 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c index 5b0918b..0c682a6 100644 --- a/src/drivers/intel/ptt/ptt.c +++ b/src/drivers/intel/ptt/ptt.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <soc/pci_devs.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c index 7d7d54c..8bbfe0a 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga_early.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga_early.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index cfb9c90..54ac50a 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,7 +3,7 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H -#include <arch/mmio.h> +#include <device/mmio.h> #include <arch/cpu.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/dedede/fw_config.c b/src/mainboard/google/dedede/fw_config.c index 7e5d8fa..6252617 100644 --- a/src/mainboard/google/dedede/fw_config.c +++ b/src/mainboard/google/dedede/fw_config.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <bootstate.h> #include <fw_config.h> #include <gpio.h> diff --git a/src/mainboard/google/dedede/variants/bugzzy/ramstage.c b/src/mainboard/google/dedede/variants/bugzzy/ramstage.c index 7844b6e..7053c30 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/ramstage.c +++ b/src/mainboard/google/dedede/variants/bugzzy/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootstate.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <delay.h> #include <bootmode.h> #include <device/device.h> diff --git a/src/mainboard/protectli/vault_bsw/mainboard.c b/src/mainboard/protectli/vault_bsw/mainboard.c index 3c9c45c..78e79c4 100644 --- a/src/mainboard/protectli/vault_bsw/mainboard.c +++ b/src/mainboard/protectli/vault_bsw/mainboard.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <device/device.h> #include <soc/iomap.h> diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index d305427..d8a8f50 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <hsio.h> #include <gpio_defs.h> diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 7befa4a..3ba173a 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <baseboard/variants.h> #include <console/console.h> #include <device/dram/common.h> diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 71a0609..6c199ad 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/bootblock.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <assert.h> #include <device/pci_ops.h> #include <types.h> diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index b88062d..6df720a 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <cbfs.h> #include <cpu/x86/cr.h> diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index e3fcb5e..9b4aa80 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 744b05e..2c90b5f 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <bootmem.h> #include <bootstate.h> #include <cbfs.h> diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index e045c9d..8c74e70 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/x86/cr.h> diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index f0bcef6..cc0e548 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -5,7 +5,7 @@ #include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <cpu/amd/cpuid.h> #include <cpu/amd/msr.h> diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c index 58b957d..96a6e420 100644 --- a/src/soc/amd/common/block/psp/psb.c +++ b/src/soc/amd/common/block/psp/psb.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <bootstate.h> #include <amdblocks/reset.h> #include <amdblocks/smn.h> diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index eacd5f6..72cf33a 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/psp_efs.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <assert.h> #include <boot_device.h> #include <commonlib/region.h> diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 4a8482e..c938623 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -4,7 +4,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/psp_efs.h> #include <amdblocks/spi.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 839d7c0..32d5e5b 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -7,7 +7,7 @@ #include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <cpu/amd/cpuid.h> #include <cpu/amd/msr.h> #include <cpu/cpu.h> diff --git a/src/soc/intel/alderlake/bootblock/update_descriptor.c b/src/soc/intel/alderlake/bootblock/update_descriptor.c index 9c8ce9c..693b285 100644 --- a/src/soc/intel/alderlake/bootblock/update_descriptor.c +++ b/src/soc/intel/alderlake/bootblock/update_descriptor.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <cf9_reset.h> #include <commonlib/region.h> #include <console/console.h> diff --git a/src/southbridge/intel/lynxpoint/uart_init.c b/src/southbridge/intel/lynxpoint/uart_init.c index 66b9e01..c8c6343 100644 --- a/src/southbridge/intel/lynxpoint/uart_init.c +++ b/src/southbridge/intel/lynxpoint/uart_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <assert.h> #include <console/uart.h> #include <device/pci_def.h> diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 5b40721..b74a8cd 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -4,7 +4,7 @@ #ifndef INTELTOOL_H #define INTELTOOL_H 1 -#include <arch/mmio.h> +#include <device/mmio.h> #include <commonlib/helpers.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/70291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Gerrit-Change-Number: 70291 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [for test] crossgcc: Update GCC from 11.2 to 12.2
by Elyes Haouas (Code Review) 04 Dec '22

04 Dec '22

Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67821 to look at the new patch set (#12). Change subject: [for test] crossgcc: Update GCC from 11.2 to 12.2 ...................................................................... [for test] crossgcc: Update GCC from 11.2 to 12.2 Change-Id: Ic02d5680929b56ad357c3a010cff7e1540001911 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/arm64/armv8/mmu.c M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-11.2.0_gnat.patch R util/crossgcc/patches/gcc-12.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-12.2.0_asan_shadow_offset_callback.patch A util/crossgcc/patches/gcc-12.2.0_gnat.patch R util/crossgcc/patches/gcc-12.2.0_libcpp.patch R util/crossgcc/patches/gcc-12.2.0_libgcc.patch D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-12.2.0.tar.xz.cksum 10 files changed, 60 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/67821/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/67821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02d5680929b56ad357c3a010cff7e1540001911 Gerrit-Change-Number: 67821 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[master]: [test] Update libgnat
by Elyes Haouas (Code Review) 04 Dec '22

04 Dec '22

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70283 ) Change subject: [test] Update libgnat ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/70283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7545be873ecd28dfb78c03ab39ba699f4af21979 Gerrit-Change-Number: 70283 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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