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Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70262 )
Change subject: drivers/wifi/generic: Fix properties in generic-under-PCI device case
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/70262/comment/8870c42c_8a73f1b4
PS4, Line 585: wifi_pcie_fill_ssdt
`wifi_pcie_fill_ssdt` should only be used for PCIe wifi, e.g.
```
device ref pcie_rp4 on
# PCIe 4 WLAN
register "pch_pcie_rp[PCH_RP(4)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
end
```
For the devicetree snippet in your commit message, it should be using `wifi_cnvi_fill_ssdt`. I.e. `wifi_generic_enable` should return `wifi_cnvi_ops`. Could you check why that's not happening?
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Change subject: src/ec/intel: Create common code for board_id implementation
......................................................................
Patch Set 5: Code-Review+2
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Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
Patch Set 5:
(7 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/70a97ffb_77887ed3
PS5, Line 20: Please share your feedback/suggestions and tell about other useful patches,
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/a3325a26_6b635a27
PS5, Line 23: 1) "board-specific": Lenovo G505S discrete GPU support, custom SeaBIOS options,
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/95cc8f9f_1a429dcb
PS5, Line 24: example configs for G505S / AM1I-A / A88XM-E and known good AtomBIOS ROMs,
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/2360805c_6e87e4d6
PS5, Line 25: and also good IRQ routing for AMD Lenovo G505S, ASUS A88XM-E and AM1I-A boards.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/63bf2425_2d2be236
PS5, Line 29: MichalOS, Snowdrop, Fiwix, Memtest (5.31b and 6.00), Tatos, Plop, FloppyBird.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/9c158db3_3588b80e
PS5, Line 31: Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
File csb_patcher.sh:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165211):
https://review.coreboot.org/c/coreboot/+/64873/comment/62baa5e9_fb24adba
PS5, Line 759: printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n"
'README' may be misspelled - perhaps 'README'?
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I'd like you to reexamine a change. Please visit
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Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
Conveniently and securely gets, checks SHA256 and installs some of my
patches from this page - https://review.coreboot.org/q/status:open+banon
- and also gets a collection of useful floppy-based operating systems.
Sometimes it takes quite a long time to get a patch merged, while the
people might need it today! - and this script could be really helpful.
It asks a [Y/N] question for every addition, and since there are some
"universal" patches as well as great floppies, you may still want to
run this script - even if your board is not Lenovo G505S or not AMD.
Please share your feedback/suggestions and tell about other useful patches,
preferably the "universal" ones - i.e. SeaBIOS. Currently included:
1) "board-specific": Lenovo G505S discrete GPU support, custom SeaBIOS options,
example configs for G505S / AM1I-A / A88XM-E and known good AtomBIOS ROMs,
and also good IRQ routing for AMD Lenovo G505S, ASUS A88XM-E and AM1I-A boards.
2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies,
smbios_mptable_768; and also a floppies collection: KolibriOS, FreeDOS,
MichalOS, Snowdrop, Fiwix, Memtest (5.31b and 6.00), Tatos, Plop, FloppyBird.
Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information.
Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2
---
A csb_patcher.sh
1 file changed, 967 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/64873/5
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Hello build bot (Jenkins), awokd(a)danwin1210.me, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols
......................................................................
src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols
Some platforms like Lenovo G505S have the motherboard versions
with the onboard AMD discrete GPU without its own dedicated EEPROM
storage for VGA Option ROM. For such a discrete GPU to be usable
with coreboot, the PCI init of GPUs has to be done differently.
These AMD_DGPU_WITHOUT_EEPROM symbols can help for such cases.
Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d
Signed-off-by: Mike Banon <mike.banon(a)3mdeb.com>
---
M src/device/Kconfig
1 file changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/57319/7
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Change subject: src/ec/intel: Create common code for board_id implementation
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Patchset-5 renames the function get_board_id -> get_rvp_board_id
This is to resolve the build conflict due to multiple function def of get_board_id across the older rvp platforms.
Will create CL to align the board_id specific implementation of older platforms with the common code format. Please do help in progressing CB:70227
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I'd like you to reexamine a change. Please visit
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Change subject: src/ec/intel: Create common code for board_id implementation
......................................................................
src/ec/intel: Create common code for board_id implementation
This patch creates initial common code structure for board_id
implementation for intel rvp platforms. Board_id helps in
identifying the platform with respect to CHROME_EC and INTEL_EC
(Windows_EC). Changes include
1. Create initial board_id.c and board_id.h
2. Modify the Makefile to include src/ec/intel directory
BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0
---
M Makefile.inc
A src/ec/intel/Makefile.inc
A src/ec/intel/board_id.c
A src/ec/intel/board_id.h
4 files changed, 48 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/70227/5
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Change subject: amdfwtool: Allow the location to be a relative address
......................................................................
Patch Set 2:
(6 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193):
https://review.coreboot.org/c/coreboot/+/69856/comment/f89cf3be_15c070cd
PS2, Line 2380: case 0xFA0000: /* Fall through */
Prefer 'fallthrough;' over fallthrough comment
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PS2, Line 2381: case 0xF20000: /* Fall through */
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PS2, Line 2382: case 0xE20000: /* Fall through */
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PS2, Line 2383: case 0xC20000: /* Fall through */
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PS2, Line 2384: case 0x820000: /* Fall through */
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PS2, Line 2385: case 0x020000: /* Fall through */
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