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Change subject: drivers/wifi/generic: Fix properties in generic-under-PCI device case
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/70262/comment/41172b3c_3aceee56
PS4, Line 585: wifi_pcie_fill_ssdt
> You might just need something like CB:67566 for ADL-P.
Correct but this is an attempt to fix an issue with the existing code where wifi/generic can handle an integrated WiFi (CNVi) device as a PCIe WiFi device and a Generic device (refer to wifi_generic_enable()).
I have verified this patch for both the cases. Refer to SSDT snippet at the end of the commit message ("SSDT when CNVi").
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Change subject: soc/intel: Adopt new common/pmbase
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/70050/comment/c1bc97d7_0d340cc8
PS5, Line 563:
> There was a patch to get rind of this extra space (CB:69806)
Done
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Change subject: sb/intel/common: Rename and inline {read,write}_pmbaseX()
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/southbridge/intel/common/pmbase.h:
https://review.coreboot.org/c/coreboot/+/70049/comment/a3905d4f_82caea8d
PS4, Line 14: #elif CONFIG(TCO_SPACE_NOT_YET_SPLIT)
: /* Must let TCO registers 0x60..0x80 through. */
: #define PMSIZE 0x80
: #elif CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)
: /* TCO registers 0x60..0x80 moved, these are now GPEs. */
: #define PMSIZE 0x80
> Well removal of TCO_SPACE_NOT_YET_SPLIT is already in the queue. […]
OK, fine with me either way.
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Change subject: /: Include <device/mmio.h> instead of <arch/mmio.h>
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/70291/comment/98230b89_fe3b60b3
PS2, Line 7: /
This might be misleading. I suggest using `treewide` instead
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Change subject: nb/intel: Set DMAR IOAPIC entry based on hardware
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
File src/northbridge/intel/haswell/acpi.c:
https://review.coreboot.org/c/coreboot/+/70269/comment/8e65bf9b_11820b9f
PS6, Line 42: PCH_IOAPIC_PCI_BUS,
Looks like a line break here.
File src/northbridge/intel/sandybridge/acpi.c:
https://review.coreboot.org/c/coreboot/+/70269/comment/7658383f_66414c94
PS6, Line 46: PCH_IOAPIC_PCI_BUS,
Line too long?
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Change subject: soc/intel: Set IO APIC DMAR entry based on hw
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
Patchset:
PS6:
I cherry-picked this train and tested on mc_ehl1 (Elkhart Lake) by comparing the DMAR ACPI table which is created at runtime (acpidump & iasl -d). The table remains unchanged (beside the time stamp) with this patch train.
I just wonder now: shall we remove 'acpi_create_dmar_ds_ioapic' completely (maybe in a follow-up) as it is not used anymore (after this patch train).
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Change subject: Enable VBOOT_VBNV_FLASH for 2065X and 206AX
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165215):
https://review.coreboot.org/c/coreboot/+/70296/comment/bb4e09d1_5d42491c
PS3, Line 28: [1] https://issuetracker.google.com/issues/235293589
Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 6c2568f4f58b ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config")'
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Hello build bot (Jenkins), Angel Pons, Alexander Couzens,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70296
to look at the new patch set (#3).
Change subject: Enable VBOOT_VBNV_FLASH for 2065X and 206AX
......................................................................
Enable VBOOT_VBNV_FLASH for 2065X and 206AX
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for boards using CPU_INTEL_MODEL_206AX.
Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for
CPU_INTEL_HASWELL, CPU_INTEL_MODEL_206AX and others (see [2]). However,
there seems to be no particular reason on those platforms. We've dropped
the config for haswell. Now do the same for CPU_INTEL_MODEL_206AX, so
that VBOOT_VBNV_FLASH can be enabled.
VBOOT_VBNV_FLASH is enabled for the following boards:
- Google boards: butterfly, link, lumpy, parrot, stout, stumpy. Use the
unused flash space for RW_NVRAM.
- Lenovo boards: t410, t420, t420s, t430, t430s, t520, t530, x131e
x1_carbon_gen1, x201, x220, x230. A 0x2000 RW_NVRAM region is
allocated for them, with the COREBOOT size reduced by 0x2000.
Also remove a VBOOT_VBNV_CMOS comment in emeraldlake2 Kconfig.
[1] https://issuetracker.google.com/issues/235293589
[2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 (CB:45740)
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
BUG=b:235293589
TEST=./util/abuild/abuild -t LENOVO_T430S -a (with VBOOT enabled)
Change-Id: I833edd4f7a328b21e81c971ba8a9aec0aad7d3d3
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_206ax/Kconfig
M src/mainboard/google/butterfly/Kconfig
M src/mainboard/google/butterfly/chromeos.fmd
M src/mainboard/google/link/Kconfig
M src/mainboard/google/link/chromeos.fmd
M src/mainboard/google/parrot/Kconfig
M src/mainboard/google/parrot/chromeos.fmd
M src/mainboard/google/stout/Kconfig
M src/mainboard/google/stout/chromeos.fmd
M src/mainboard/intel/emeraldlake2/Kconfig
M src/mainboard/lenovo/t410/Kconfig
M src/mainboard/lenovo/t410/vboot-rwa.fmd
M src/mainboard/lenovo/t420/Kconfig
M src/mainboard/lenovo/t420/vboot-rwa.fmd
M src/mainboard/lenovo/t420s/Kconfig
M src/mainboard/lenovo/t420s/vboot-rwa.fmd
M src/mainboard/lenovo/t430/Kconfig
M src/mainboard/lenovo/t430/vboot-rwab.fmd
M src/mainboard/lenovo/t430s/Kconfig
M src/mainboard/lenovo/t430s/vboot-rwab.fmd
M src/mainboard/lenovo/t520/Kconfig
M src/mainboard/lenovo/t520/vboot-rwa.fmd
M src/mainboard/lenovo/t530/Kconfig
M src/mainboard/lenovo/t530/vboot-rwab.fmd
M src/mainboard/lenovo/x131e/Kconfig
M src/mainboard/lenovo/x131e/vboot-rwab.fmd
M src/mainboard/lenovo/x1_carbon_gen1/Kconfig
M src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd
M src/mainboard/lenovo/x201/Kconfig
M src/mainboard/lenovo/x201/vboot-rwa.fmd
M src/mainboard/lenovo/x220/Kconfig
M src/mainboard/lenovo/x220/vboot-rwa.fmd
M src/mainboard/lenovo/x230/Kconfig
M src/mainboard/lenovo/x230/vboot-rwab.fmd
M src/mainboard/samsung/lumpy/Kconfig
M src/mainboard/samsung/lumpy/chromeos.fmd
M src/mainboard/samsung/stumpy/Kconfig
M src/mainboard/samsung/stumpy/chromeos.fmd
39 files changed, 82 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70296/3
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Yu-Ping Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/70295 )
Change subject: mb/hp/z220_series: Drop VBOOT support
......................................................................
mb/hp/z220_series: Drop VBOOT support
There is no .fmd file with RW regions for z220_series, which is required
for VBOOT. Therefore, the VBOOT option is useless for z220_series. In
fact, HP_Z220_CMT_WORKSTATION doesn't even build with VBOOT:
E: Image is missing 'GBB' region
Remove the VBOOT Kconfig option from z220_series.
BUG=b:235293589
TEST=none
Change-Id: I9dcabda5e8ee3a0084736d3674dca31d1f5a641f
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M Documentation/security/vboot/list_vboot.md
M src/mainboard/hp/z220_series/Kconfig
2 files changed, 21 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/70295/2
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