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[M] Change in coreboot[master]: soc/mediatek: Fix DSI register definition for MT8186
by Rex-BC Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Liju-Clr Chen, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70183 ) Change subject: soc/mediatek: Fix DSI register definition for MT8186 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70183/comment/9bc06f39_018a616f PS1, Line 10: version versions -- To view, visit https://review.coreboot.org/c/coreboot/+/70183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Gerrit-Change-Number: 70183 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:52:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Add MIPI panel support for firmware display
by Rex-BC Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70181 ) Change subject: soc/mediatek/mt8188: Add MIPI panel support for firmware display ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Gerrit-Change-Number: 70181 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:51:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Add DSI support
by Liju-Clr Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Rex-BC Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70184 to review the following change. Change subject: soc/mediatek/mt8188: Add DSI support ...................................................................... soc/mediatek/mt8188: Add DSI support For MT8188, we need to add DSI and MIPI_TX setting to support MIPI panel. BUG=b:244208960 TEST=emerge-geralt coreboot build pass Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/include/soc/addressmap.h A src/soc/mediatek/mt8188/include/soc/dsi.h 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/70184/1 diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 59ec553..7ac988b 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index da95952..a5a3c00 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -77,6 +77,7 @@ I2C3_BASE = IO_PHYS + 0x01282000, SFLASH_REG_BASE = IO_PHYS + 0x0132C000, IOCFG_RM_BASE = IO_PHYS + 0x01C00000, + MIPITX_BASE = IO_PHYS + 0x01C80000, I2C1_BASE = IO_PHYS + 0x01E00000, I2C4_BASE = IO_PHYS + 0x01E01000, IOCFG_LT_BASE = IO_PHYS + 0x01E10000, @@ -95,6 +96,7 @@ DISP_AAL0_BASE = IO_PHYS + 0x0C005000, DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, + DSI0_BASE = IO_PHYS + 0x0C008000, DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, DP_INTF0_BASE = IO_PHYS + 0x0C015000, DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, diff --git a/src/soc/mediatek/mt8188/include/soc/dsi.h b/src/soc/mediatek/mt8188/include/soc/dsi.h new file mode 100644 index 0000000..1a4eab4 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dsi.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8188_DSI_H +#define SOC_MEDIATEK_MT8188_DSI_H + +#include <soc/dsi_common.h> +#include <soc/dsi_register_v2.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Gerrit-Change-Number: 70184 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/mediatek: Fix DSI register definition for MT8186
by Liju-Clr Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Rex-BC Chen. Hello Rex-BC Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70183 to review the following change. Change subject: soc/mediatek: Fix DSI register definition for MT8186 ...................................................................... soc/mediatek: Fix DSI register definition for MT8186 The DSI CMDQ offset for MT8186 is different from previous SoCs. Therefore, we define two version for DSI register header files. The v1 is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188. BUG=b:244208960 TEST=build pass BRANCH=corsola Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/dsi_common.h A src/soc/mediatek/common/include/soc/dsi_register_v1.h A src/soc/mediatek/common/include/soc/dsi_register_v2.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/mediatek/mt8186/include/soc/dsi.h M src/soc/mediatek/mt8192/include/soc/dsi.h 7 files changed, 134 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/70183/1 diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index bc4bfa1..a0acce8 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -45,53 +45,8 @@ MIPI_DSI_MODE_LINE_END = BIT(12), }; -struct dsi_regs { - u32 dsi_start; - u8 reserved0[4]; - u32 dsi_inten; - u32 dsi_intsta; - u32 dsi_con_ctrl; - u32 dsi_mode_ctrl; - u32 dsi_txrx_ctrl; - u32 dsi_psctrl; - u32 dsi_vsa_nl; - u32 dsi_vbp_nl; - u32 dsi_vfp_nl; - u32 dsi_vact_nl; - u32 dsi_lfr_con; /* Available since MT8183 */ - u32 dsi_lfr_sta; /* Available since MT8183 */ - u32 dsi_size_con; /* Available since MT8183 */ - u32 dsi_vfp_early_stop; /* Available since MT8183 */ - u32 reserved1[4]; - u32 dsi_hsa_wc; - u32 dsi_hbp_wc; - u32 dsi_hfp_wc; - u32 dsi_bllp_wc; - u32 dsi_cmdq_size; - u32 dsi_hstx_cklp_wc; - u8 reserved2[156]; - u32 dsi_phy_lccon; - u32 dsi_phy_ld0con; - u8 reserved3[4]; - u32 dsi_phy_timecon0; - u32 dsi_phy_timecon1; - u32 dsi_phy_timecon2; - u32 dsi_phy_timecon3; - u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[92]; - u32 dsi_force_commit; /* Available since MT8183 */ - u8 reserved6[108]; - u32 dsi_cmdq[128]; -}; static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -check_member(dsi_regs, dsi_phy_lccon, 0x104); -check_member(dsi_regs, dsi_phy_timecon3, 0x11c); -check_member(dsi_regs, dsi_vm_cmd_con, 0x130); -check_member(dsi_regs, dsi_force_commit, 0x190); -check_member(dsi_regs, dsi_cmdq, 0x200); - /* DSI_INTSTA */ enum { LPRX_RD_RDY_INT_FLAG = BIT(0), diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v1.h b/src/soc/mediatek/common/include/soc/dsi_register_v1.h new file mode 100644 index 0000000..ec5dfda --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dsi_register_v1.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DSI_REGISTER_V1_H +#define DSI_REGISTER_V1_H + +#include <commonlib/helpers.h> +#include <soc/addressmap.h> +#include <types.h> + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; /* Available since MT8183 */ + u32 dsi_lfr_sta; /* Available since MT8183 */ + u32 dsi_size_con; /* Available since MT8183 */ + u32 dsi_vfp_early_stop; /* Available since MT8183 */ + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; /* Available since MT8183 */ + u8 reserved6[108]; + u32 dsi_cmdq[128]; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq, 0x200); + +#endif /* DSI_REGISTER_V1_H */ diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v2.h b/src/soc/mediatek/common/include/soc/dsi_register_v2.h new file mode 100644 index 0000000..17809c7 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dsi_register_v2.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DSI_REGISTER_V2_H +#define DSI_REGISTER_V2_H + +#include <commonlib/helpers.h> +#include <soc/addressmap.h> +#include <types.h> + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; /* Available since MT8183 */ + u32 dsi_lfr_sta; /* Available since MT8183 */ + u32 dsi_size_con; /* Available since MT8183 */ + u32 dsi_vfp_early_stop; /* Available since MT8183 */ + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; /* Available since MT8183 */ + u8 reserved6[2924]; + u32 dsi_cmdq[128]; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq, 0xd00); + +#endif /* DSI_REGISTER_V2_H */ diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 6f9b301..22010c9 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -4,6 +4,7 @@ #define _DSI_REG_H_ #include <soc/dsi_common.h> +#include <soc/dsi_register_v1.h> #include <types.h> /* DSI features */ diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 9da79e6..3fcc281 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_DSI_H #include <soc/dsi_common.h> +#include <soc/dsi_register_v1.h> #include <types.h> /* DSI features */ diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h index 2cb9159..1a7c2f99 100644 --- a/src/soc/mediatek/mt8186/include/soc/dsi.h +++ b/src/soc/mediatek/mt8186/include/soc/dsi.h @@ -9,6 +9,7 @@ #define SOC_MEDIATEK_MT8186_DSI_H #include <soc/dsi_common.h> +#include <soc/dsi_register_v2.h> /* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 100 diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h index ed3d0d8..9ce55fa 100644 --- a/src/soc/mediatek/mt8192/include/soc/dsi.h +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_DSI_H #include <soc/dsi_common.h> +#include <soc/dsi_register_v1.h> /* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 100 -- To view, visit https://review.coreboot.org/c/coreboot/+/70183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Gerrit-Change-Number: 70183 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by build bot (Jenkins) (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 74: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164966): https://review.coreboot.org/c/coreboot/+/68471/comment/0826caf7_ef4ea7bf PS74, Line 14: mode. Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/soc/amd/common/acpi/dptc.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164966): https://review.coreboot.org/c/coreboot/+/68471/comment/b19cb461_f47eaf50 PS74, Line 34: #if CONFIG(FEATURE_DYNAMIC_DPTC) trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 74 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:47:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Add MIPI panel support for firmware display
by Liju-Clr Chen (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Rex-BC Chen. Hello Rex-BC Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70181 to review the following change. Change subject: soc/mediatek/mt8188: Add MIPI panel support for firmware display ...................................................................... soc/mediatek/mt8188: Add MIPI panel support for firmware display For geralt project, we also support MIPI panel as our firmware display. So add this patch to configure ddp to choose eDP display or MIPI panel display. BUG=b:244208960 TEST=test firmware display pass for both eDP and MIPI panel on MT8188 EVB. Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> --- M src/mainboard/google/geralt/display.c M src/soc/mediatek/mt8188/ddp.c M src/soc/mediatek/mt8188/include/soc/ddp.h 3 files changed, 55 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/70181/1 diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 3db9171..eaee6c8 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -55,7 +55,7 @@ edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_mode_set(&edid); + mtk_ddp_mode_set(&edid, DISP_PATH_EDP); info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); if (info) fb_set_orientation(info, LB_FB_ORIENTATION_NORMAL); diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c index 8d2d43a..ce14fa7 100644 --- a/src/soc/mediatek/mt8188/ddp.c +++ b/src/soc/mediatek/mt8188/ddp.c @@ -6,24 +6,36 @@ #include <soc/addressmap.h> #include <soc/ddp.h> -static void disp_config_main_path_connection(void) +static void disp_config_main_path_connection(enum disp_path_sel path) { /* ovl0 */ write32(&mmsys_cfg->mmsys_ovl_mout_en, DISP_OVL0_TO_DISP_RDMA0); - write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, - SEL_IN_DP_INTF0_FROM_DISP_DITHER0); - write32(&mmsys_cfg->mmsys_dither0_sel_out, - SEL_OUT_DISP_DITHER0_TO_DP_INTF0); + + if (path == DISP_PATH_EDP) { + write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, + SEL_IN_DP_INTF0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DP_INTF0); + } else { + write32(&mmsys_cfg->mmsys_dsi0_sel_in, + SEL_IN_DSI0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DSI0); + } } -static void disp_config_main_path_mutex(void) +static void disp_config_main_path_mutex(enum disp_path_sel path) { write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); - /* Clock source from DP_INTF0 */ - write32(&disp_mutex->mutex[0].ctl, - MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + if (path == DISP_PATH_EDP) + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + else + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 7)); + write32(&disp_mutex->mutex[0].en, BIT(0)); } @@ -94,7 +106,7 @@ write32(&regs->en, PQ_EN); } -static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh, enum disp_path_sel path) { u32 idx; const u32 pixel_clk = width * height * vrefresh; @@ -114,8 +126,8 @@ gamma_config(width, height); postmask_config(width, height); dither_config(width, height); - disp_config_main_path_connection(); - disp_config_main_path_mutex(); + disp_config_main_path_connection(path); + disp_config_main_path_mutex(path); } static void disp_clock_on(void) @@ -133,7 +145,7 @@ write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; @@ -156,7 +168,7 @@ __func__, vrefresh); } - main_disp_path_setup(width, height, vrefresh); + main_disp_path_setup(width, height, vrefresh, path); rdma_start(); ovl_layer_config(fmt, bpp, width, height); } diff --git a/src/soc/mediatek/mt8188/include/soc/ddp.h b/src/soc/mediatek/mt8188/include/soc/ddp.h index 26f0151..475485e 100644 --- a/src/soc/mediatek/mt8188/include/soc/ddp.h +++ b/src/soc/mediatek/mt8188/include/soc/ddp.h @@ -82,7 +82,8 @@ CG_CON0_DISP_AAL0 | CG_CON0_DISP_GAMMA0 | CG_CON0_DISP_DITHER0 | - CG_CON0_DISP_DP_INTF0, + CG_CON0_DISP_DP_INTF0 | + CG_CON0_DISP_DSI0, CG_CON0_ALL = 0xffffffff }; @@ -122,7 +123,8 @@ CG_CON2_DPI_DPI0 = BIT(8), CG_CON2_DP_INTF0 = BIT(16), - CG_CON2_DISP_ALL = CG_CON2_DP_INTF0, + CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | + CG_CON2_DP_INTF0, CG_CON2_ALL = 0xffffffff }; @@ -280,7 +282,12 @@ SMI_LARB_PORT_L0_OVL_RDMA0 = 0xF88, }; +enum disp_path_sel { + DISP_PATH_EDP = 0, + DISP_PATH_MIPI, +}; + void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Gerrit-Change-Number: 70181 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
by Elyes Haouas (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Paul Menzel, Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69700/comment/3e4e6c1d_4581f48f PS7, Line 8: > Please add the comment back. Done Patchset: PS11: Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 01 Dec 2022 05:22:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
by Elyes Haouas (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Arthur Heymans, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69700 to look at the new patch set (#11). Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 ...................................................................... crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6 Tested with BUILD_TIMELESS=1: binaries stay the same for qemu-i440fx. Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum 11 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69700/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Dinesh Gehlot (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70172 to look at the new patch set (#5). Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of commit 7c6dd796f26f (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/70172/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 5 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Update cpu and pch tracehub modes
by Sridhar Siricilla (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Subrata Banik, Maulik Vaghela, Paul Menzel. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64438 ) Change subject: soc/intel/alderlake: Update cpu and pch tracehub modes ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Need to understand what is the path forward with this patch trend ? Do you still want to block the Patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/64438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Gerrit-Change-Number: 64438 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 04:37:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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