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Change subject: util/amdfwtool: Deal with psp position in flash offset directly
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69852/comment/7725f481_91f0a6e1
PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION))
> > I agree with what Karthik's saying here. […]
"The PSP really only cares about flash offsets, not x86 mmap offsets."
Christopher told me that this is not entirely true. There is a settings field in the image which allows you to set which mode it operates in, e.g. flash offset mode or x86 mmap offset I think. Though I'm not sure if the amdfwtool sets this or what the default mode was.
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Change subject: mb/amd/birman: Add EC fw to flash
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
BIRMAN_EC_POSITION
This variable is dependent on the existence of fmap_config.h and can not be set when the CBFS of ecfw is defined.
Anyone can give a sollution?
Thanks.
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Change subject: amdfwtool: Add new family morgana & glinda
......................................................................
Patch Set 10:
(2 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/69046/comment/48f19bf0_bfdecd19
PS8, Line 1937: morgana and
> since morgana is now handled in the code, please remove it from the TODO here
Done
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/69046/comment/d11a850a_4cb35e87
PS9, Line 707: 0xBC0E0200
> 0xBC0D0B00?
Done
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Change subject: /: Include <device/mmio.h> instead of <arch/mmio.h>
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
If you change it from arch to device you should take care of the right include order then (sort it correctly).
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Change subject: soc/intel/elkhartlake: Move TCO_NO_REBOOT flag support
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
> If there is a PCI device not supporting bus-mastering and the related PCI command register bit is ha […]
OK, looking into a few other intel platforms showed that when this bit is not defined it is reserved, so far I have not seen a different function bound to this bit. I am OK with doing it this way, though we should take an eye on it for future platforms.
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Change subject: drivers/wifi/generic: Fix properties in generic-under-PCI device case
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/70262/comment/41172b3c_3aceee56
PS4, Line 585: wifi_pcie_fill_ssdt
> You might just need something like CB:67566 for ADL-P.
Correct but this is an attempt to fix an issue with the existing code where wifi/generic can handle an integrated WiFi (CNVi) device as a PCIe WiFi device and a Generic device (refer to wifi_generic_enable()).
I have verified this patch for both the cases. Refer to SSDT snippet at the end of the commit message ("SSDT when CNVi").
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Change subject: soc/intel: Adopt new common/pmbase
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/70050/comment/c1bc97d7_0d340cc8
PS5, Line 563:
> There was a patch to get rind of this extra space (CB:69806)
Done
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Change subject: sb/intel/common: Rename and inline {read,write}_pmbaseX()
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/southbridge/intel/common/pmbase.h:
https://review.coreboot.org/c/coreboot/+/70049/comment/a3905d4f_82caea8d
PS4, Line 14: #elif CONFIG(TCO_SPACE_NOT_YET_SPLIT)
: /* Must let TCO registers 0x60..0x80 through. */
: #define PMSIZE 0x80
: #elif CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)
: /* TCO registers 0x60..0x80 moved, these are now GPEs. */
: #define PMSIZE 0x80
> Well removal of TCO_SPACE_NOT_YET_SPLIT is already in the queue. […]
OK, fine with me either way.
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Change subject: /: Include <device/mmio.h> instead of <arch/mmio.h>
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/70291/comment/98230b89_fe3b60b3
PS2, Line 7: /
This might be misleading. I suggest using `treewide` instead
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Change subject: nb/intel: Set DMAR IOAPIC entry based on hardware
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
File src/northbridge/intel/haswell/acpi.c:
https://review.coreboot.org/c/coreboot/+/70269/comment/8e65bf9b_11820b9f
PS6, Line 42: PCH_IOAPIC_PCI_BUS,
Looks like a line break here.
File src/northbridge/intel/sandybridge/acpi.c:
https://review.coreboot.org/c/coreboot/+/70269/comment/7658383f_66414c94
PS6, Line 46: PCH_IOAPIC_PCI_BUS,
Line too long?
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