Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53894 )
Change subject: soc/mediatek/mt8195: Add i2c driver support
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/mt8195/i2c.c:
https://review.coreboot.org/c/coreboot/+/53894/comment/641f0639_aa514f4c
PS3, Line 109: gpio_set_mode(ptr[i].gpio, ptr[i].func);
> I'll try to reproduce it locally.
I can not reproduce this issue from my local environment.
After reviewing the driver, I also don't think the issue will occur..
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Hello build bot (Jenkins), Raul Rangel, Matt DeVillier, Stefan Reinauer, Angel Pons, Piotr Król, Jason Glenesk, Tarun Tuli, Michał Żygowski, Subrata Banik, Werner Zeh, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: treewide: Include <device/mmio.h> instead of <arch/mmio.h>
......................................................................
treewide: Include <device/mmio.h> instead of <arch/mmio.h>
<device/mmio.h>` chain-include `<arch/mmio.h>.
Also sort includes while on it.
Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/device/xhci.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/intel/ptt/ptt.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/include/cpu/x86/lapic.h
M src/mainboard/google/dedede/fw_config.c
M src/mainboard/google/dedede/variants/bugzzy/ramstage.c
M src/mainboard/protectli/vault_bsw/mainboard.c
M src/mainboard/scaleway/tagada/hsio.c
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
M src/northbridge/intel/x4x/bootblock.c
M src/security/intel/txt/common.c
M src/security/intel/txt/logging.c
M src/security/intel/txt/ramstage.c
M src/security/intel/txt/romstage.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_efs.c
M src/soc/amd/common/block/spi/fch_spi.c
M src/soc/amd/picasso/agesa_acpi.c
M src/soc/intel/alderlake/bootblock/update_descriptor.c
M src/southbridge/intel/lynxpoint/uart_init.c
22 files changed, 50 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/70291/3
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70291 )
Change subject: /: Include <device/mmio.h> instead of <arch/mmio.h>
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/70291/comment/35eb339f_d79de2b6
PS2, Line 7: /
> This might be misleading. […]
Done
Patchset:
PS2:
> If you change it from arch to device you should take care of the right include order then (sort it c […]
Done
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Change subject: util/amdfwtool: Deal with psp position in flash offset directly
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69852/comment/7725f481_91f0a6e1
PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION))
> > I agree with what Karthik's saying here. […]
"The PSP really only cares about flash offsets, not x86 mmap offsets."
Christopher told me that this is not entirely true. There is a settings field in the image which allows you to set which mode it operates in, e.g. flash offset mode or x86 mmap offset I think. Though I'm not sure if the amdfwtool sets this or what the default mode was.
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Change subject: mb/amd/birman: Add EC fw to flash
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
BIRMAN_EC_POSITION
This variable is dependent on the existence of fmap_config.h and can not be set when the CBFS of ecfw is defined.
Anyone can give a sollution?
Thanks.
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Change subject: amdfwtool: Add new family morgana & glinda
......................................................................
Patch Set 10:
(2 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/69046/comment/48f19bf0_bfdecd19
PS8, Line 1937: morgana and
> since morgana is now handled in the code, please remove it from the TODO here
Done
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/69046/comment/d11a850a_4cb35e87
PS9, Line 707: 0xBC0E0200
> 0xBC0D0B00?
Done
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Change subject: /: Include <device/mmio.h> instead of <arch/mmio.h>
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
If you change it from arch to device you should take care of the right include order then (sort it correctly).
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Change subject: soc/intel/elkhartlake: Move TCO_NO_REBOOT flag support
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
> If there is a PCI device not supporting bus-mastering and the related PCI command register bit is ha […]
OK, looking into a few other intel platforms showed that when this bit is not defined it is reserved, so far I have not seen a different function bound to this bit. I am OK with doing it this way, though we should take an eye on it for future platforms.
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