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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162 )
Change subject: security/tpm: support compiling in multiple TPM drivers
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69162/comment/52a4922d_80b6e224
PS7, Line 12: Making probe functions static and always using them uncovered that
: bootblock stage included TPM driver which it didn't use. This is why
: Makefile.inc files were updated to replace `all-*` with
: romstage, ramstage and verstage.
> (Apparently my yesterday's reply to this was somehow lost. […]
TPM is also setup in verstage which doesn't have to be a separate stage and may run/start in bootblock instead. Then I think the drivers might be needed.
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Change subject: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable
......................................................................
Patch Set 2: Code-Review+2
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Hello Marc Jones,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70348
to look at the new patch set (#2).
Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
......................................................................
soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
Add fast_spi_set_bde() to be called by the SOC lockdown function.
The lock is SOC specific, so it can't be called in common PCH lockdown
function.
Change-Id: I3f7cca671250996a6be7b5b28437c3e1bf777678
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/70348/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70348 )
Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165227):
https://review.coreboot.org/c/coreboot/+/70348/comment/174d66b8_9d349a8e
PS1, Line 9: Add fast_spi_set_bde() to be called by the SOC lockdown function.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68944 )
Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/oc_wdt/Kconfig:
https://review.coreboot.org/c/coreboot/+/68944/comment/f22d5bff_d9a00da6
PS7, Line 10: HAVE_CF9_RESET_PREPARE
> This seems wrong to me. […]
Any other ideas how to hook into reset functions? Create yet another hook?
The reason behind hooking into reset is to distinguish from expected resets and unexpected resets.
Also we can ignore this as well and do not implement any unexpected reset detection logic for now.
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Hello Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70346
to look at the new patch set (#3).
Change subject: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
......................................................................
mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
This patch adds the initial code for mtlrvp_p variant board
which includes
1. support for 2 mainboards (Chrome EC and Windows EC) by
adding overridetree.cb to corresponding directory
2. Move devicetree to baseboard/mtlrvp
3. Update mainboard name in Kconfig and Kconfig.name
4. Add config option to select corresponding overridetree.cb
BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89
---
M src/mainboard/intel/mtlrvp/Kconfig
M src/mainboard/intel/mtlrvp/Kconfig.name
R src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb
A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb
A src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
5 files changed, 38 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/70346/3
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Christopher Meis has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 )
Change subject: util/amdfwtool: Deal with psp position in flash offset directly
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69852/comment/fc12b8e2_200fb00e
PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION))
> "The PSP really only cares about flash offsets, not x86 mmap offsets." […]
This also is not exactly correct.
When looking for the EFS location, the PSP only cares about flash offsets.
In EFT, again, addresses to PSP and BIOS directories are set in flash offsets.
PSP and BIOS directory headers have a indicator to provide information about address mode to expect from each entry. Entries inherit this information if not overwritten by entry configuration from the outside/user.
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Hello Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70346
to look at the new patch set (#2).
Change subject: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
......................................................................
mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
This patch adds the initial code for mtlrvp_p variant board
which includes
1. support for 2 mainboards (Chrome EC and Windows EC) by
adding overridetree.cb to corresponding directory
2. Move devicetree to baseboard/mtlrvp
3. Update mainboard name in Kconfig and Kconfig.name
4. Add config option to select corresponding overridetree.cb
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89
---
M src/mainboard/intel/mtlrvp/Kconfig
M src/mainboard/intel/mtlrvp/Kconfig.name
R src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb
A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb
A src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
5 files changed, 34 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/70346/2
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