coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

1 participants
6828 discussions

[M] Change in coreboot[master]: nb/intel/i945: Remove apic 0 from devicetree
by Felix Held (Code Review) 05 Dec '22

05 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69299 ) ( 15 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/i945: Remove apic 0 from devicetree ...................................................................... nb/intel/i945: Remove apic 0 from devicetree This is added at runtime. Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb 9 files changed, 24 insertions(+), 55 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index a7832ef..dd701da 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -13,13 +13,7 @@ register "gpu_panel_power_backlight_off_delay" = "2380" register "gpu_panel_power_cycle_delay" = "2" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end - + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" device domain 0 on diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 8238826..f6d5f76 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -2,12 +2,7 @@ chip northbridge/intel/i945 - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster device domain 0 on ops i945_pci_domain_ops diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 2514ad4..b12335e 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -5,12 +5,7 @@ register "gfx.ndid" = "2" register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 51ca420..611bd96 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -2,12 +2,7 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 5c72c72..4007e7e 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -2,12 +2,7 @@ chip northbridge/intel/i945 - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_441 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index e58d8f3..cd67480 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -2,12 +2,7 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7a9e9ae..913b732 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -13,12 +13,7 @@ register "gpu_panel_power_backlight_off_delay" = "2380" register "gpu_panel_power_cycle_delay" = "2" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index a41749a..d7c86a5 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -13,12 +13,7 @@ register "gpu_panel_power_backlight_off_delay" = "2380" register "gpu_panel_power_cycle_delay" = "2" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index eb0bdcd..a3b00c1 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -4,12 +4,7 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end # APIC cluster register "pci_mmio_size" = "768" -- To view, visit https://review.coreboot.org/c/coreboot/+/69299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Gerrit-Change-Number: 69299 Gerrit-PatchSet: 19 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: nb/intel/x4x: Remove apic 0 from devicetree
by Felix Held (Code Review) 05 Dec '22

05 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69298 ) Change subject: nb/intel/x4x: Remove apic 0 from devicetree ...................................................................... nb/intel/x4x: Remove apic 0 from devicetree This is added at runtime. Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb 18 files changed, 34 insertions(+), 108 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index 1f2bc08..94067a6 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x8086 0x0028 inherit diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 28b24d8..3eeeafd 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 7daa4a4..3b1f7fa 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index a5d205c..c041c63 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 83fc040..a89388f 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 0dbe8d9..353e80b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index d7d4655..4b1d290 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index d6dbc2d..b1b0106 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb index f099ab2..602ef02 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 54f9dcf..6e7d142 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index f099ab2..602ef02 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 8e061f2..a8982f1 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on # Host Bridge diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 602ba57..b70a6af 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index af15577..b63d204 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -1,12 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 5ec31eb..4f6d900 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 06617f6..49d6f8b 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 80d2bf7..c33509b 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x8086 0x0028 inherit diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index a8dea8d..4afbec9 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x17aa 0x304f inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/69298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Gerrit-Change-Number: 69298 Gerrit-PatchSet: 19 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: nb/intel/x4x: Remove apic 0 from devicetree
by Felix Held (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Stefan Ott, Angel Pons, Arthur Heymans, Alexander Couzens. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69298 ) Change subject: nb/intel/x4x: Remove apic 0 from devicetree ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Gerrit-Change-Number: 69298 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Mon, 05 Dec 2022 14:22:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
by Felix Held (Code Review) 05 Dec '22

05 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69297 ) Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ...................................................................... cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/cpu/intel/model_1067x/chip.h M src/cpu/intel/model_1067x/model_1067x_init.c M src/include/cpu/intel/speedstep.h M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb M src/mainboard/asus/p5ql-em/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/northbridge/intel/gm45/chip.h M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c 33 files changed, 101 insertions(+), 124 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h deleted file mode 100644 index b298615..0000000 --- a/src/cpu/intel/model_1067x/chip.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -struct cpu_intel_model_1067x_config { - int c5 : 1; - int c6 : 1; - int slfm : 1; -}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 02e6032..825a246 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -9,25 +9,18 @@ #include <cpu/x86/name.h> #include <cpu/intel/smm_reloc.h> -#include "chip.h" - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - const struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - /* Is C5 requested and supported? */ - const int c5 = conf && conf->c5 && + const int c5 = southbridge_support_c5() && (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); /* Is C6 requested and supported? */ - const int c6 = conf && conf->c6 && + const int c6 = southbridge_support_c6() && ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ @@ -75,14 +68,9 @@ { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - msr = rdmsr(MSR_EXTENDED_CONFIG); /* Super LFM supported? */ - if (conf && conf->slfm && (msr.lo & (1 << 27))) + if (northbridge_support_slfm() && (msr.lo & (1 << 27))) msr.lo |= (1 << 28); /* Enable Super LFM. */ wrmsr(MSR_EXTENDED_CONFIG, msr); diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index e085e34..1a31c25 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -3,11 +3,9 @@ #ifndef CPU_INTEL_SPEEDSTEP_H #define CPU_INTEL_SPEEDSTEP_H +#include <stdbool.h> #include <stdint.h> -/* Magic value used to locate speedstep configuration in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - /* MWAIT coordination I/O base address. This must match * the \_PR_.CP00 PM base address. */ @@ -92,4 +90,8 @@ #define SPEEDSTEP_MIN_POWER_PENRYN 15000 #define SPEEDSTEP_SLFM_POWER_PENRYN 12000 +bool southbridge_support_c5(void); +bool southbridge_support_c6(void); +bool northbridge_support_slfm(void); + #endif /* CPU_INTEL_SPEEDSTEP_H */ diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index 713ac40..1f2bc08 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 846a02b..28b24d8 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 8115430..7daa4a4 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ef019d1..a5d205c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 4237041..83fc040 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 23268f2b..0dbe8d9 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index a9cad93..8238826 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -7,9 +7,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x - device lapic 0xACAC off end - end end device domain 0 on diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index c452672..d7d4655 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index b0452d4..d6dbc2d 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb index 8390bc0..f099ab2 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 70e82e8..54f9dcf 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 8390bc0..f099ab2 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index a839b9d..8e061f2 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 1044851..602ba57 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 46bb422..af15577 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 673172d..5064cd9 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -7,9 +7,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x - device lapic 0xACAC off end - end end register "pci_mmio_size" = "768" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 3a4ae45..5ec31eb 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 641ada5..06617f6 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 5e2eb9d..80d2bf7 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xacac off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 0bfdbc9..7946e34 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -8,22 +8,13 @@ register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms + register "slfm" = "1" + device cpu_cluster 0 on ops gm45_cpu_bus_ops chip cpu/intel/socket_p device lapic 0 on end end - chip cpu/intel/model_1067x - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - # Enable Super LFM - register "slfm" = "1" - - # Enable C5, C6 - register "c5" = "1" - register "c6" = "1" - end end register "pci_mmio_size" = "2048" diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index 9a2c452..a8dea8d 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -6,9 +6,6 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index dc059f0..814491b 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -8,22 +8,13 @@ register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms + register "slfm" = "1" + device cpu_cluster 0 on ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end - chip cpu/intel/model_1067x - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - # Enable Super LFM - register "slfm" = "1" - - # Enable C5, C6 - register "c5" = "1" - register "c6" = "1" - end end register "pci_mmio_size" = "2048" diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index d4b4aef..bb2cd70 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -1,22 +1,12 @@ chip northbridge/intel/gm45 # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "slfm" = "1" device cpu_cluster 0 on ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end - chip cpu/intel/model_1067x - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - # Enable Super LFM - register "slfm" = "1" - - # Enable C5, C6 - register "c5" = "1" - register "c6" = "1" - end end register "pci_mmio_size" = "2048" diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 0d09bb4..76cecca 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -19,6 +19,7 @@ * Maximum PCI mmio size in MiB. */ u16 pci_mmio_size; + int slfm; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 31e3de4..c6fa0e0 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -7,6 +7,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci_def.h> @@ -257,3 +258,10 @@ CHIP_NAME("Intel GM45 Northbridge") .init = gm45_init, }; + +bool northbridge_support_slfm(void) +{ + struct device *gmch = __pci_0_00_0; + struct northbridge_intel_gm45_config *config = gmch->chip_info; + return config->slfm == 1; +} diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index c175576..0027656 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -10,6 +10,7 @@ #include <device/pci_ids.h> #include <acpi/acpi.h> #include <cpu/intel/smm_reloc.h> +#include <cpu/intel/speedstep.h> #include "i945.h" static void mch_domain_read_resources(struct device *dev) @@ -164,3 +165,8 @@ struct chip_operations northbridge_intel_i945_ops = { CHIP_NAME("Intel i945 Northbridge") }; + +bool northbridge_support_slfm(void) +{ + return false; +} diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index da046d1..cfa57ad 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -12,6 +12,7 @@ #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/intel/smm_reloc.h> +#include <cpu/intel/speedstep.h> static void mch_domain_read_resources(struct device *dev) { @@ -194,3 +195,8 @@ CHIP_NAME("Intel 4-Series Northbridge") .init = x4x_init, }; + +bool northbridge_support_slfm(void) +{ + return false; +} diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index fd0a203..69c1469 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/speedstep.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -473,3 +474,13 @@ .vendor = PCI_VID_INTEL, .devices = pci_device_ids, }; + +bool southbridge_support_c5(void) +{ + return false; +} + +bool southbridge_support_c6(void) +{ + return false; +} diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 24b8a27..d897130 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/speedstep.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -137,6 +138,20 @@ pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } +bool southbridge_support_c5(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; + return config->c5_enable == 1; +} + +bool southbridge_support_c6(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; + return config->c6_enable == 1; +} + static void i82801ix_power_options(struct device *dev) { u8 reg8; @@ -216,15 +231,15 @@ reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only if (CONFIG(DEBUG_PERIODIC_SMI)) reg16 |= (3 << 0); // Periodic SMI every 8s - if (config->c5_enable) + if (southbridge_support_c5()) reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); /* Set exit timings for C5/C6. */ - if (config->c5_enable) { + if (southbridge_support_c5()) { reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); reg8 &= ~((7 << 3) | (7 << 0)); - if (config->c6_enable) + if (southbridge_support_c6()) reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, 95-102us DPRSTP# to STP_CPU# */ else diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 39b662a..ead2b8a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -13,6 +13,7 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> +#include <cpu/intel/speedstep.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include "chip.h" @@ -139,6 +140,20 @@ pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } +bool southbridge_support_c5(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info; + return config->c5_enable == 1; +} + +bool southbridge_support_c6(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info; + return config->c6_enable == 1; +} + static void i82801jx_power_options(struct device *dev) { u8 reg8; @@ -218,15 +233,15 @@ reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only if (CONFIG(DEBUG_PERIODIC_SMI)) reg16 |= (3 << 0); // Periodic SMI every 8s - if (config->c5_enable) + if (southbridge_support_c5()) reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); /* Set exit timings for C5/C6. */ - if (config->c5_enable) { + if (southbridge_support_c5()) { reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); reg8 &= ~((7 << 3) | (7 << 0)); - if (config->c6_enable) + if (southbridge_support_c6()) reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, 95-102us DPRSTP# to STP_CPU# */ else -- To view, visit https://review.coreboot.org/c/coreboot/+/69297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Gerrit-Change-Number: 69297 Gerrit-PatchSet: 19 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/zork: Select VBOOT by default
by Felix Held (Code Review) 05 Dec '22

05 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69763 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/zork: Select VBOOT by default ...................................................................... mb/google/zork: Select VBOOT by default Zork boards will not boot without PSP verstage/VBOOT, so select it by default. Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69763 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/Kconfig 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index d483999..68c5ba1 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -107,6 +107,9 @@ default y if USE_AMD_BLOBS config VBOOT + bool + # selected by default as PSP verstage required for booting at present time + default y select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH select VBOOT_STARTS_BEFORE_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/69763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9 Gerrit-Change-Number: 69763 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/nvidia/tegra210: Fix flushing SPI fifo
by Felix Held (Code Review) 05 Dec '22

05 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70137 ) Change subject: soc/nvidia/tegra210: Fix flushing SPI fifo ...................................................................... soc/nvidia/tegra210: Fix flushing SPI fifo This will avoid clearing the other bits in fifo_status. Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/nvidia/tegra210/spi.c 1 file changed, 16 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 0f38df2..e6f667a 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -331,7 +331,7 @@ uint32_t fifo_status = read32(&spi->regs->fifo_status); fifo_status |= flush_mask; - write32(&spi->regs->fifo_status, flush_mask); + write32(&spi->regs->fifo_status, fifo_status); while (read32(&spi->regs->fifo_status) & flush_mask) ; -- To view, visit https://review.coreboot.org/c/coreboot/+/70137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Gerrit-Change-Number: 70137 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: commonlib/helpers.h: use unsigned literals in definitions
by Krystian Hebel (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Kyösti Mälkki, Sergii Dmytruk. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70106 ) Change subject: commonlib/helpers.h: use unsigned literals in definitions ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Does this force all arithmetic involving KiB to use 64bit arithmetic? For i386 builds too? Not all, only those that would eventually end up in 64bit variable. Compilers are allowed to use smaller width if it doesn't change the result, and even skip multiplication entirely or change the multiplier if it can be calculated at the time of compilation. Nevertheless, result of multiplication on i386 is returned in `%edx:%eax`, so it already is 64bit wide. -- To view, visit https://review.coreboot.org/c/coreboot/+/70106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60a6ee82db80328e44639175272cc8097f36c3b Gerrit-Change-Number: 70106 Gerrit-PatchSet: 3 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 14:19:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device
by Tarun Tuli (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Eran Mitrani, Subrata Banik, Kapil Porwal, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70266 ) Change subject: mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551 Gerrit-Change-Number: 70266 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 14:08:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/poppy: Add support for a variant finalize function
by Subrata Banik (Code Review) 05 Dec '22

05 Dec '22

1 0

[L] Change in coreboot[master]: soc/intel/{adl, common}: provide a list of D-states to enter LPM
by Subrata Banik (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Tarun Tuli, Eran Mitrani, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/{adl, common}: provide a list of D-states to enter LPM ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/139a1816_b175ce3a PS9, Line 31: LPI_REVISION_0 > imho, I think it's important to have them incase anyone ever adds other things. In these cases, these values have specific meanings (values) in the specification and if someone inserts something, we could now be sending across the wrong values. > > @subrata, wdyt? Sure, please add those enum value explicitly as Tarun suggested. (i'm okay with it) -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 12 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 14:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2022