Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70055 )
Change subject: util/genbuild_h: Update version calculation
......................................................................
util/genbuild_h: Update version calculation
- 'git describe --match [0-9].[0-9]*' was giving me an error, so use
the basic 'git describe' command instead.
- If a .coreboot-version file exists, use that to determine the version.
This fixes the problem for coreboot releases.
- Don't run git for the versions unless it's being built from a valid
git repository. Use 0.0 as the default version for timeless or unknown.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I5fae2f012cc9b9914d8803af8dd58a885358cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70055
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M util/genbuild_h/genbuild_h.sh
1 file changed, 34 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, but someone else must approve
Jakub Czapiga: Looks good to me, approved
diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh
index 8c72ddf..78b09a6 100755
--- a/util/genbuild_h/genbuild_h.sh
+++ b/util/genbuild_h/genbuild_h.sh
@@ -6,6 +6,9 @@
GITREV=""
TIMESOURCE=""
XGCCPATH="${XGCCPATH:-util/crossgcc/xgcc/bin/}"
+MAJOR_VER="0"
+MINOR_VER="0"
+COREBOOT_VERSION_FILE=".coreboot-version"
export LANG=C
export LC_ALL=C
@@ -32,10 +35,17 @@
GITREV=$(get_git_head_data %h)
TIMESOURCE=git
DATE=$(get_git_head_data %ct)
+ VERSION="$(git describe)"
+ MAJOR_VER="$(echo "${VERSION}" | sed 's/\([0-9]\)\.\([0-9][0-9]*\).*/\1/')"
+ MINOR_VER="$(echo "${VERSION}" | sed 's/\([0-9]\)\.\([0-9][0-9]*\).*/\2/')"
else
GITREV=Unknown
TIMESOURCE="date"
- DATE=$(LANG= LC_ALL=C TZ=UTC0 date +%s)
+ DATE=$(LANG="" LC_ALL=C TZ=UTC0 date +%s)
+ if [ -f "${COREBOOT_VERSION_FILE}" ]; then
+ MAJOR_VER="$(sed 's/\([0-9]\)\.\([0-9][0-9]*\).*/\1/' "${COREBOOT_VERSION_FILE}")"
+ MINOR_VER="$(sed 's/\([0-9]\)\.\([0-9][0-9]*\).*/\2/' "${COREBOOT_VERSION_FILE}")"
+ fi
fi
our_date() {
@@ -70,7 +80,8 @@
printf "#define COREBOOT_ORIGIN_GIT_REVISION \"$GITREV\"\n"
printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION"
-printf "#define COREBOOT_MAJOR_VERSION %d\n#define COREBOOT_MINOR_VERSION %d\n" `git describe --match [0-9].[0-9]* | sed 's/\([0-9]\)\.\([0-9][0-9]*\).*/\1 \2/'`
+printf "#define COREBOOT_MAJOR_VERSION %d\n" "${MAJOR_VER}"
+printf "#define COREBOOT_MINOR_VERSION %d\n" "${MINOR_VER}"
printf "#define COREBOOT_BUILD \"$(our_date "$DATE")\"\n"
printf "#define COREBOOT_BUILD_YEAR_BCD 0x$(our_date "$DATE" +%y)\n"
printf "#define COREBOOT_BUILD_MONTH_BCD 0x$(our_date "$DATE" +%m)\n"
--
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Gerrit-Change-Id: I5fae2f012cc9b9914d8803af8dd58a885358cb1a
Gerrit-Change-Number: 70055
Gerrit-PatchSet: 2
Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69534 )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/tigerlake: Fix setting `HyperThreading`
......................................................................
soc/intel/tigerlake: Fix setting `HyperThreading`
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.
Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 22 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Felix Singer: Looks good to me, approved
Sean Rhodes: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6e15d50..c34892a 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -432,9 +432,6 @@
*/
uint8_t cpu_ratio_override;
- /* HyperThreadingDisable : Yes (1) / No (0) */
- uint8_t HyperThreadingDisable;
-
/*
* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the DMI Power Optimizer.
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 399cb87..d4e694e 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -125,9 +125,6 @@
m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2);
m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3);
- /* Hyper Threading */
- m_cfg->HyperThreading = !config->HyperThreadingDisable;
-
/* Disable Lock PCU Thermal Management registers */
m_cfg->LockPTMregs = 0;
/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
--
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Gerrit-Change-Number: 69534
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Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
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Attention is currently required from: Martin L Roth.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70110 )
Change subject: [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator
......................................................................
Patch Set 4:
(2 comments)
File ssdtgen/Makefile.inc:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165243):
https://review.coreboot.org/c/coreboot/+/70110/comment/7d92051f_11082d25
PS4, Line 3: # Set all necesary paths. Remember that .SECONDEXPANSION is enabled,
'necesary' may be misspelled - perhaps 'necessary'?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165243):
https://review.coreboot.org/c/coreboot/+/70110/comment/ef4d7ea4_61a04723
PS4, Line 137: # Clear ramstage sources to prevent generation of unnecesary resipes in main Makefile
'unnecesary' may be misspelled - perhaps 'unnecessary'?
--
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Gerrit-Change-Id: I78766cd1f47e24b2cd7f9b5cf1cca066441ead06
Gerrit-Change-Number: 70110
Gerrit-PatchSet: 4
Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Jan Dabros <jsd(a)semihalf.com>
Gerrit-CC: Noga Smith <nogasmith(a)google.com>
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Gerrit-Comment-Date: Mon, 05 Dec 2022 14:36:34 +0000
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Attention is currently required from: Martin L Roth.
Hello build bot (Jenkins), Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70110
to look at the new patch set (#4).
Change subject: [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator
......................................................................
[WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator
Work in progress.
TODO:
- Documentation
- Dynamic/config-based mocks
- Modular devicetree (multi-override in sconfig?)
- Cleanup
BUG=b:161391394
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I78766cd1f47e24b2cd7f9b5cf1cca066441ead06
---
M Makefile
A ssdtgen/Makefile.inc
A ssdtgen/devicetree.cb
A ssdtgen/fw_config.c
A ssdtgen/mock/fsp/util.h
A ssdtgen/mock/gpio.c
A ssdtgen/mock/soc/gpio.h
A ssdtgen/mock/soc/nvs.h
A ssdtgen/ssdtgen.h
A ssdtgen/ssdtgen_main.c
A ssdtgen/ssdtgen_sys.c
11 files changed, 458 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/70110/4
--
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Gerrit-Change-Number: 70110
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Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com>
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Hello Martin L Roth, Jan Dabros,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70359
to look at the new patch set (#2).
Change subject: tests/Makefile.inc: Build utilities in separate directory
......................................................................
tests/Makefile.inc: Build utilities in separate directory
Utilities like kconfig/conf now will be built inside tests build tree.
It will eliminate possible colisions of target names when using test
framework in more than one place (see CB:70110)
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I4c1eb901c921f4ec6ee8985b154362153c5fd0e7
---
M tests/Makefile.inc
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/70359/2
--
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Gerrit-Change-Number: 70359
Gerrit-PatchSet: 2
Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
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Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com>
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Hello Martin L Roth, Jan Dabros,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70298
to look at the new patch set (#2).
Change subject: tests/Makefile.common: Remove unnecessary dependency to kconfig/conf
......................................................................
tests/Makefile.common: Remove unnecessary dependency to kconfig/conf
Utility will be built while executing kconfig targets so it is not
necessary to keep hard dependency on kconfig here.
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I578f3e1d9de63e91ded44746539265bcd55bf579
---
M tests/Makefile.common
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/70298/2
--
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Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com>
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Gerrit-MessageType: newpatchset
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70206 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/amd/mayan: Improve naming of EC FW
......................................................................
mb/amd/mayan: Improve naming of EC FW
Change the EC FW CBFS filename prefix to a more accurate "ec/"
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/amd/mayan/Kconfig
M src/mainboard/amd/mayan/Makefile.inc
2 files changed, 20 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/mainboard/amd/mayan/Kconfig b/src/mainboard/amd/mayan/Kconfig
index 8a54481..8cd412a 100644
--- a/src/mainboard/amd/mayan/Kconfig
+++ b/src/mainboard/amd/mayan/Kconfig
@@ -78,7 +78,7 @@
depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
# Add the EFS and EC to the RO region only
# This is a mayan-specific override of soc/amd/morgana/Kconfig
- default "apu/amdfw apu/ecfw"
+ default "apu/amdfw ec/ecfw"
config CHROMEOS
# Use default libpayload config
diff --git a/src/mainboard/amd/mayan/Makefile.inc b/src/mainboard/amd/mayan/Makefile.inc
index fdf00ea..20d6f4b 100644
--- a/src/mainboard/amd/mayan/Makefile.inc
+++ b/src/mainboard/amd/mayan/Makefile.inc
@@ -25,10 +25,10 @@
$(call int-subtract, 0xffffffff \
$(CONFIG_ROM_SIZE)) $(CONFIG_MAYAN_MCHP_FW_OFFSET) 1)
-cbfs-files-y += apu/ecfw
-apu/ecfw-file := $(CONFIG_MAYAN_MCHP_FW_FILE)
-apu/ecfw-position := $(MAYAN_EC_POSITION)
-apu/ecfw-type := raw
+cbfs-files-y += ec/ecfw
+ec/ecfw-file := $(CONFIG_MAYAN_MCHP_FW_FILE)
+ec/ecfw-position := $(MAYAN_EC_POSITION)
+ec/ecfw-type := raw
else
files_added:: warn_no_mchp
--
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Gerrit-Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed
Gerrit-Change-Number: 70206
Gerrit-PatchSet: 3
Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70216 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: google/skyrim/Kconfig: Enable DPTC for Morthal
......................................................................
google/skyrim/Kconfig: Enable DPTC for Morthal
Enable SOC_AMD_COMMON_BLOCK_ACPI_DPTC for Morthal boards, to enable
support for the low/no battery boot feature.
BUG=b:217911928
TEST=build_packages --board=skyrim chromeos-bootimage --autosetgov
Change-Id: I3eb6bee6601e34420a90f33f8f2c45cf3fe37f9b
Signed-off-by: Tim Van Patten <timvp(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70216
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/skyrim/Kconfig.name
1 file changed, 20 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name
index 8bfbe3f..67bbd45 100644
--- a/src/mainboard/google/skyrim/Kconfig.name
+++ b/src/mainboard/google/skyrim/Kconfig.name
@@ -13,6 +13,7 @@
config BOARD_GOOGLE_MORTHAL
bool "-> Morthal"
select BOARD_GOOGLE_BASEBOARD_SKYRIM
+ select SOC_AMD_COMMON_BLOCK_ACPI_DPTC
config BOARD_GOOGLE_FROSTFLOW
bool "-> Frostflow"
--
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Gerrit-Owner: Tim Van Patten <timvp(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
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