coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

1 participants
6828 discussions

[S] Change in coreboot[master]: nb/intel/sandybridge: Use write32p()
by Angel Pons (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70293 ) Change subject: nb/intel/sandybridge: Use write32p() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520 Gerrit-Change-Number: 70293 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 05 Dec 2022 10:56:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
by Harsha B R (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P. Hello Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70346 to look at the new patch set (#3). Change subject: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board ...................................................................... mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board This patch adds the initial code for mtlrvp_p variant board which includes 1. support for 2 mainboards (Chrome EC and Windows EC) by adding overridetree.cb to corresponding directory 2. Move devicetree to baseboard/mtlrvp 3. Update mainboard name in Kconfig and Kconfig.name 4. Add config option to select corresponding overridetree.cb BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Kconfig.name R src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 5 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/70346/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 Gerrit-Change-Number: 70346 Gerrit-PatchSet: 3 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by Shuming Chu (Shuming) (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Marc Jones. Hello Marc Jones, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70348 to review the following change. Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... soc/intel/common/block/fast_spi: Add SPI BIOS decode lock Add fast_spi_set_bde() to be called by the SOC lockdown function. The lock is SOC specific, so it can't be called in common PCH lockdown function. Change-Id: I3f7cca671250996a6be7b5b28437c3e1bf777678 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/70348/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 471c85d..9735a84 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -458,6 +458,16 @@ pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl); } +void fast_spi_set_bde(void) +{ + const pci_devfn_t dev = PCH_DEV_SPI; + uint32_t bde; + + bde = pci_read_config32(dev, SPI_BIOS_DECODE_EN); + bde |= SPI_BIOS_DECODE_LOCK; + pci_write_config32(dev, SPI_BIOS_DECODE_EN, bde); +} + void fast_spi_clear_outstanding_status(void) { void *spibar = fast_spi_get_bar(); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 4012c29..af46ccb 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -4,6 +4,8 @@ #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H /* PCI configuration registers */ +#define SPI_BIOS_DECODE_EN 0xd8 +#define SPI_BIOS_DECODE_LOCK BIT(31) #define SPI_BIOS_CONTROL 0xdc diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 90f1cb2..681e66c 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -103,5 +103,9 @@ */ struct postcar_frame; void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf); +/* + * Set FAST_SPIBAR BIOS Decode Lock bit. + */ +void fast_spi_set_bde(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/70348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f7cca671250996a6be7b5b28437c3e1bf777678 Gerrit-Change-Number: 70348 Gerrit-PatchSet: 1 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Christopher Meis (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth, Fred Reitberger, Marvin Drees, Karthik Ramasubramanian, Felix Held. Christopher Meis has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/fc12b8e2_200fb00e PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) > "The PSP really only cares about flash offsets, not x86 mmap offsets." […] This also is not exactly correct. When looking for the EFS location, the PSP only cares about flash offsets. In EFT, again, addresses to PSP and BIOS directories are set in flash offsets. PSP and BIOS directory headers have a indicator to provide information about address mode to expect from each entry. Entries inherit this information if not overwritten by entry configuration from the outside/user. -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Christopher Meis <christopher.meis(a)9elements.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Dec 2022 10:51:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Marvin Drees <marvin.drees(a)9elements.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
by Harsha B R (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P. Hello Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70346 to look at the new patch set (#2). Change subject: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board ...................................................................... mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board This patch adds the initial code for mtlrvp_p variant board which includes 1. support for 2 mainboards (Chrome EC and Windows EC) by adding overridetree.cb to corresponding directory 2. Move devicetree to baseboard/mtlrvp 3. Update mainboard name in Kconfig and Kconfig.name 4. Add config option to select corresponding overridetree.cb Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Kconfig.name R src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 5 files changed, 34 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/70346/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 Gerrit-Change-Number: 70346 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Makefile.inc: fix multiple jobs build issue
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Martin L Roth, Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69819 ) Change subject: Makefile.inc: fix multiple jobs build issue ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69819/comment/51dbc048_43b8abb6 PS2, Line 12: Workaround > Work around Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a70beedf2eb1c018c5ff98163904253f9a87a61 Gerrit-Change-Number: 69819 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 05 Dec 2022 10:47:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Makefile.inc: fix multiple jobs build issue
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Michał Żygowski, Martin L Roth. Hello build bot (Jenkins), Nico Huber, Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69819 to look at the new patch set (#3). Change subject: Makefile.inc: fix multiple jobs build issue ...................................................................... Makefile.inc: fix multiple jobs build issue Certain C source files for coreboot stages require fmap_config.h to be present. When building coreboot using multiple jobs the dependency is not always satisfied due to race condition and results in make error. Work around it by adding fmap_config.h to stage C deps. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3a70beedf2eb1c018c5ff98163904253f9a87a61 --- M Makefile.inc 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/69819/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a70beedf2eb1c018c5ff98163904253f9a87a61 Gerrit-Change-Number: 69819 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: amdfwtool: Add new family morgana & glinda
by ritul guru (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69046 ) Change subject: amdfwtool: Add new family morgana & glinda ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Gerrit-Change-Number: 69046 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Dec 2022 09:36:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board
by Harsha B R (Code Review) 05 Dec '22

05 Dec '22

Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70346 ) Change subject: mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board ...................................................................... mb/intel/mtlrvp: Add initial code for mtlrvp_p variant board This patch adds the initial code for mtlrvp_p variant board which includes 1. support for 2 mainboards (Chrome EC and Windows EC) by adding overridetree.cb to corresponding directory 2. Move devicetree to baseboard/mtlrvp 3. Update mainboard name in Kconfig and Kconfig.name 4. Add config option to select corresponding overridetree.cb Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Kconfig.name R src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 5 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/70346/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index db7c161..b6c0561 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -8,6 +8,9 @@ config BOARD_INTEL_MTLRVP_P select BOARD_INTEL_MTLRVP_COMMON +config BOARD_INTEL_MTLRVP_P_EXT_EC + select BOARD_INTEL_MTLRVP_COMMON + if BOARD_INTEL_MTLRVP_COMMON config MAINBOARD_DIR @@ -31,6 +34,7 @@ config VARIANT_DIR string default "mtlrvp_p" if BOARD_INTEL_MTLRVP_P + default "mtlrvp_p_ext_ec" if BOARD_INTEL_MTLRVP_P_EXT_EC config DEVICETREE string diff --git a/src/mainboard/intel/mtlrvp/Kconfig.name b/src/mainboard/intel/mtlrvp/Kconfig.name index b643b94..e14c628 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig.name +++ b/src/mainboard/intel/mtlrvp/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_INTEL_MTLRVP_P bool "Meteorlake-P RVP" + +config BOARD_INTEL_MTLRVP_P_EXT_EC + bool "Meteorlake-P RVP with Chrome EC" diff --git a/src/mainboard/intel/mtlrvp/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb similarity index 100% rename from src/mainboard/intel/mtlrvp/devicetree.cb rename to src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/devicetree.cb diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb new file mode 100644 index 0000000..7ca0024 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/meteorlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb new file mode 100644 index 0000000..7ca0024 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/meteorlake + + device domain 0 on end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/70346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 Gerrit-Change-Number: 70346 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: arm64: mmu: Spot check security state for TTB mapping
by Hung-Te Lin (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Julius Werner. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28017 ) Change subject: arm64: mmu: Spot check security state for TTB mapping ...................................................................... Patch Set 2: (1 comment) File src/arch/arm64/armv8/mmu.c: https://review.coreboot.org/c/coreboot/+/28017/comment/b170db55_606c3b32 PS2, Line 324: assert_correct_ttb_mapping(_ettb - 1); > that gives me using gcc-12.2: […] Well, this should be a false alert. Although I'm not sure how what's the best way to fix it - changing to `_ttb + REGION_SIZE(ttb) - 1` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/28017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70cda4f76f201b03d69a9ece063a3830b15ac04b Gerrit-Change-Number: 28017 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 05 Dec 2022 09:25:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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coreboot-gerrit December 2022