coreboot-gerrit December 2022

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[S] Change in coreboot[master]: soc/intel/common/block: Use readXXp/writeXXp()
by Elyes Haouas (Code Review) 04 Dec '22

04 Dec '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70294 ) Change subject: soc/intel/common/block: Use readXXp/writeXXp() ...................................................................... soc/intel/common/block: Use readXXp/writeXXp() Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/block/xhci/elog.c M src/soc/intel/common/block/xhci/xhci.c 6 files changed, 24 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/70294/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 2bc7cf1..f896cd9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -42,7 +42,7 @@ uint16_t reg) { uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, sizeof(uint32_t)); - return read32((void *)addr); + return read32p(addr); } /* Write to register in FAST_SPI flash controller. */ @@ -50,7 +50,7 @@ uint16_t reg, uint32_t val) { uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, sizeof(uint32_t)); - write32((void *)addr, val); + write32p(addr, val); } /* @@ -378,7 +378,7 @@ /* Find first empty FPR */ for (fpr = 0; fpr < SPIBAR_FPR_MAX; fpr++) { - reg = read32((void *)fpr_base); + reg = read32p(fpr_base); if (reg == 0) break; fpr_base += sizeof(uint32_t); @@ -408,8 +408,8 @@ reg = SPI_FPR(start, end) | protect_mask; /* Set the FPR register and verify it is protected */ - write32((void *)fpr_base, reg); - reg = read32((void *)fpr_base); + write32p(fpr_base, reg); + reg = read32p(fpr_base); if (!(reg & protect_mask)) { printk(BIOS_ERR, "Unable to set SPI FPR %d\n", fpr); return -1; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index dae181a..e9a6a5d 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -148,12 +148,12 @@ uint32_t graphics_gtt_read(unsigned long reg) { - return read32((void *)(graphics_get_gtt_base() + reg)); + return read32p(graphics_get_gtt_base() + reg); } void graphics_gtt_write(unsigned long reg, uint32_t data) { - write32((void *)(graphics_get_gtt_base() + reg), data); + write32p(graphics_get_gtt_base() + reg, data); } void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 395a14d..d37b330 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -283,14 +283,14 @@ uint32_t offset) { assert(p->mmio_base != 0); - return read32((void *)(p->mmio_base + offset)); + return read32p(p->mmio_base + offset); } static void gspi_write_mmio_reg(const struct gspi_ctrlr_params *p, uint32_t offset, uint32_t value) { assert(p->mmio_base != 0); - write32((void *)(p->mmio_base + offset), value); + write32p(p->mmio_base + offset, value); } static int gspi_ctrlr_params_init(struct gspi_ctrlr_params *p, diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 299f4c1..aecdfbb 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -97,8 +97,8 @@ base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), + write32p((uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32p((uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | PCIEXBAR_PCIEXBAREN); } } diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index 8acefba..2f94ba6 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -29,7 +29,7 @@ for (i = 0; i < num; i++, base += 0x10) { /* Read port status and control register for the port. */ - port_status = read32((void *)base); + port_status = read32p(base); /* Ensure that the status is not all 1s. */ if (port_status == 0xffffffff) diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index a12f875..9931fb6 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -3,6 +3,7 @@ #include <acpi/acpi_device.h> #include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/usb/acpi/chip.h> @@ -68,7 +69,7 @@ else port_sts_reg = (uintptr_t)res->base + info->usb3_port_status_reg + port_id * 0x10; - port_status = read32((void *)port_sts_reg); + port_status = read32p(port_sts_reg); /* Ensure that the status is not all 1s */ if (port_status == 0xffffffff) -- To view, visit https://review.coreboot.org/c/coreboot/+/70294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c Gerrit-Change-Number: 70294 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/ec/intel: Create common code for board_id implementation
by Harsha B R (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70227 ) Change subject: src/ec/intel: Create common code for board_id implementation ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Patchset-5 renames the function get_board_id -> get_rvp_board_id This is to resolve the build conflict due to multiple function def of get_board_id across the older rvp platforms. Will create CL to align the board_id specific implementation of older platforms with the common code format. Please do help in progressing CB:70227 -- To view, visit https://review.coreboot.org/c/coreboot/+/70227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Gerrit-Change-Number: 70227 Gerrit-PatchSet: 5 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Sun, 04 Dec 2022 13:20:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/ec/intel: Create common code for board_id implementation
by Harsha B R (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D. Hello build bot (Jenkins), Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70227 to look at the new patch set (#5). Change subject: src/ec/intel: Create common code for board_id implementation ...................................................................... src/ec/intel: Create common code for board_id implementation This patch creates initial common code structure for board_id implementation for intel rvp platforms. Board_id helps in identifying the platform with respect to CHROME_EC and INTEL_EC (Windows_EC). Changes include 1. Create initial board_id.c and board_id.h 2. Modify the Makefile to include src/ec/intel directory BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 --- M Makefile.inc A src/ec/intel/Makefile.inc A src/ec/intel/board_id.c A src/ec/intel/board_id.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/70227/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Gerrit-Change-Number: 70227 Gerrit-PatchSet: 5 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: amdfwtool: Allow the location to be a relative address
by build bot (Jenkins) (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Bao Zheng, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69856 ) Change subject: amdfwtool: Allow the location to be a relative address ...................................................................... Patch Set 2: (6 comments) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193): https://review.coreboot.org/c/coreboot/+/69856/comment/f89cf3be_15c070cd PS2, Line 2380: case 0xFA0000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193): https://review.coreboot.org/c/coreboot/+/69856/comment/7ee4c612_4f3da175 PS2, Line 2381: case 0xF20000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193): https://review.coreboot.org/c/coreboot/+/69856/comment/1e0a95a3_6c0abeec PS2, Line 2382: case 0xE20000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193): https://review.coreboot.org/c/coreboot/+/69856/comment/0777e65c_131bb613 PS2, Line 2383: case 0xC20000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193): https://review.coreboot.org/c/coreboot/+/69856/comment/eea752bc_26042c29 PS2, Line 2384: case 0x820000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165193): https://review.coreboot.org/c/coreboot/+/69856/comment/ce7ce10c_1a2f3b4e PS2, Line 2385: case 0x020000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment -- To view, visit https://review.coreboot.org/c/coreboot/+/69856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Gerrit-Change-Number: 69856 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Sun, 04 Dec 2022 11:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/birman: Add EC fw to flash
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Jason Glenesk, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70314 to review the following change. Change subject: mb/amd/birman: Add EC fw to flash ...................................................................... mb/amd/birman: Add EC fw to flash Change-Id: I2e20f399c4bfe32ec43242619628f7775b4e659e Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Makefile.inc M src/mainboard/amd/birman/board.fmd M src/mainboard/amd/birman/chromeos.fmd 4 files changed, 23 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/70314/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 412300d..8544f0a 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -60,7 +60,7 @@ config BIRMAN_MCHP_FW_OFFSET hex depends on BIRMAN_HAVE_MCHP_FW - default 0xB80000 + default 0x81000 help The EC firmware blob defaults to the 4MByte offset of the firmware image. If this offset needs to change, a new signature block must be diff --git a/src/mainboard/amd/birman/Makefile.inc b/src/mainboard/amd/birman/Makefile.inc index b0466e7..1bb6c0c 100644 --- a/src/mainboard/amd/birman/Makefile.inc +++ b/src/mainboard/amd/birman/Makefile.inc @@ -18,13 +18,16 @@ ifeq ($(CONFIG_BIRMAN_HAVE_MCHP_FW),y) $(call add_intermediate, add_mchp_fw) - $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_BIRMAN_MCHP_SIG_FILE) --fill-upward + $(CBFSTOOL) $(obj)/coreboot.pre write -r ECSIG -f $(CONFIG_BIRMAN_MCHP_SIG_FILE) --fill-upward # calculate the absolute position from the config offset -BIRMAN_EC_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(CONFIG_ROM_SIZE)) $(CONFIG_BIRMAN_MCHP_FW_OFFSET) 1) +BIRMAN_EC_POSITION=$(call int-subtract, \ + $(call _toint, $(CONFIG_BIRMAN_MCHP_FW_OFFSET)) \ + $(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_EC_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h))) +regions-for-file-apu/ecfw=EC cbfs-files-y += apu/ecfw apu/ecfw-file := $(CONFIG_BIRMAN_MCHP_FW_FILE) apu/ecfw-position := $(BIRMAN_EC_POSITION) diff --git a/src/mainboard/amd/birman/board.fmd b/src/mainboard/amd/birman/board.fmd index 21a86c0..2d222b2 100644 --- a/src/mainboard/amd/birman/board.fmd +++ b/src/mainboard/amd/birman/board.fmd @@ -1,7 +1,8 @@ FLASH@0xFE000000 32M { BIOS { - EC 4K + ECSIG 4K AMDFW(CBFS) @131008 + EC(CBFS) @512K 300K FMAP @16M 3K RW_MRC_CACHE 120K COREBOOT(CBFS) @17M diff --git a/src/mainboard/amd/birman/chromeos.fmd b/src/mainboard/amd/birman/chromeos.fmd index c28070a..235a223 100644 --- a/src/mainboard/amd/birman/chromeos.fmd +++ b/src/mainboard/amd/birman/chromeos.fmd @@ -1,6 +1,7 @@ -FLASH@0xFF000000 16M { +FLASH@0xFE000000 32M { SI_BIOS { EC 4K + AMDFW @131008 RW_MRC_CACHE(PRESERVE) 120K RW_SECTION_A 4M { VBLOCK_A 8K @@ -21,7 +22,7 @@ RW_NVRAM(PRESERVE) 20K SMMSTORE(PRESERVE) 64K RW_LEGACY(CBFS) - WP_RO@10M 6M { + WP_RO@16M 16M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K -- To view, visit https://review.coreboot.org/c/coreboot/+/70314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e20f399c4bfe32ec43242619628f7775b4e659e Gerrit-Change-Number: 70314 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: top/Makefile.inc: Define regions-for-file with a flexibility
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Martin L Roth, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70313 to review the following change. Change subject: top/Makefile.inc: Define regions-for-file with a flexibility ...................................................................... top/Makefile.inc: Define regions-for-file with a flexibility If we need to put a CBFS chunk into a specific region, add a line in any Makefile.inc regions-for-file-xxx=region_name Change-Id: Ie37a8a9230dc8b8e5664be8806f047afb94fba69 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M Makefile.inc 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/70313/1 diff --git a/Makefile.inc b/Makefile.inc index ef565c2..0c2d3c0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -814,7 +814,7 @@ # # This is the default implementation. When using a boot strategy employing # multiple CBFSes in fmap regions, override it. -regions-for-file ?= COREBOOT +regions-for-file ?= $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT) ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y) cbfs-autogen-attributes=-g -- To view, visit https://review.coreboot.org/c/coreboot/+/70313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie37a8a9230dc8b8e5664be8806f047afb94fba69 Gerrit-Change-Number: 70313 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Revert "soc/amd: Add amdfw.rom in coreboot.pre"
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/70312 to review the following change. Change subject: Revert "soc/amd: Add amdfw.rom in coreboot.pre" ...................................................................... Revert "soc/amd: Add amdfw.rom in coreboot.pre" This reverts commit 8d66fb1a7056961aaa8874d8d9001716c9a61c1b. Change-Id: Ifbfb3c88c4407fe57f30660f24208d73937f03f8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/morgana/Makefile.inc M src/soc/amd/picasso/Makefile.inc 5 files changed, 32 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/70312/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 1f2bb6d..5a1c4e1 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -273,6 +273,11 @@ --output $@ +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(CEZANNE_FWM_POSITION) +apu/amdfw-type := raw + ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index f047a59..96ea192 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -15,18 +15,6 @@ amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) -ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) -$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom - cp $< $@ - -add_bootblock = \ - $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ - -b $(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) -endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) - ifeq ($(CONFIG_VBOOT_GSCVD),y) build_complete:: $(AMDFWREAD) diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 92c75f8..30d20f7 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -304,6 +304,11 @@ --output $@ +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(MENDOCINO_FWM_POSITION) +apu/amdfw-type := raw + ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index a88e1a5..f117a4a 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -297,6 +297,11 @@ --output $@ +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(MORGANA_FWM_POSITION) +apu/amdfw-type := raw + ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 504a40e..7de6c4a 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -285,6 +285,11 @@ --anywhere \ --output $@ +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(PICASSO_FWM_POSITION) +apu/amdfw-type := raw + ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom -- To view, visit https://review.coreboot.org/c/coreboot/+/70312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbfb3c88c4407fe57f30660f24208d73937f03f8 Gerrit-Change-Number: 70312 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: WIP:mb/amd/birman: Split the amdfw.rom into head and body
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Jason Glenesk, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69922 to look at the new patch set (#2). Change subject: WIP:mb/amd/birman: Split the amdfw.rom into head and body ...................................................................... WIP:mb/amd/birman: Split the amdfw.rom into head and body Change-Id: I9d61d707c8292f7d89db5fccc26e860ff76e7374 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/board.fmd M src/soc/amd/morgana/Makefile.inc 2 files changed, 23 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/69922/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d61d707c8292f7d89db5fccc26e860ff76e7374 Gerrit-Change-Number: 69922 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: amdfwtool: Allow the amdfw.rom to be split into two parts
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Hello Marshall Dawson, Zheng Bao, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69857 to look at the new patch set (#2). Change subject: amdfwtool: Allow the amdfw.rom to be split into two parts ...................................................................... amdfwtool: Allow the amdfw.rom to be split into two parts Split the big PSP FW data into two parts, head and body. The head needs to be located at specific location. The body address is more flexible. So the EC FW can be put to the address like 0x80000. Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/morgana/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 83 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69857/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28 Gerrit-Change-Number: 69857 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: amdfwtool: Add new family morgana & glinda
by Bao Zheng (Code Review) 04 Dec '22

04 Dec '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69046 to look at the new patch set (#10). Change subject: amdfwtool: Add new family morgana & glinda ...................................................................... amdfwtool: Add new family morgana & glinda Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/69046/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Gerrit-Change-Number: 69046 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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