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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/zork/romstage.c:
https://review.coreboot.org/c/coreboot/+/51181/comment/45466fd1_0e9bc74a
PS2, Line 3: #include <baseboard/variants.h>
> I mean <console/console.h> <console/uart.h>..etc.
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson, Chris Wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51181
to look at the new patch set (#4).
Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
---
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/romstage.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/zork/variants/vilboz/Makefile.inc
A src/soc/amd/picasso/include/soc/romstage.h
M src/soc/amd/picasso/romstage.c
6 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/51181/4
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49683/comment/dc5a5faa_0bf2c010
PS6, Line 13: BRANCH=zork
> How is this tested? Maybe paste the new log messages?
Just a debug print before upload.
------------------------------------------------
image ID: AMD_PCS0, base 0x20c0000 + 0x4b000
Config region 0x46cec + 0x104
Memory init offset 0x7b8
POST: 0x34
bootmode is set to: 0
CW variant_updm_update
telemetry_vddcr_vdd_slope_mA: 32453
telemetry_vddcr_vdd_offset: 168
telemetry_vddcr_soc_slope_mA: 22644
telemetry_vddcr_soc_offset: -70
POST: 0x36
Calling FspMemoryInit: 0x020c07b8
0x02000dec: raminit_upd
0x0204d57c: &hob_list_ptr
-------------------------------------------------
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/zork/variants/vilboz/romstage.c:
https://review.coreboot.org/c/coreboot/+/49683/comment/00f37122_8a3d9773
PS6, Line 3: #include <baseboard/variants.h>
> it consumed by variant_updm_update. so keep the header file.
I mean #include <console/uart.h> #include <fw_config.h> #include <soc/pci_devs.h> #include <fw_config.h>
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 7:
(3 comments)
Patchset:
PS6:
> I would suggest call the file like variant.c not romstage. […]
it use the romstage to align picasso/romstage, and try to avoid to confuse another varinat.c but I think it's a open option.
File src/mainboard/google/zork/variants/vilboz/romstage.c:
https://review.coreboot.org/c/coreboot/+/49683/comment/ad150a62_4a202ccd
PS3, Line 22: }
> adding a line without newline at end of file
File src/mainboard/google/zork/variants/vilboz/romstage.c:
https://review.coreboot.org/c/coreboot/+/49683/comment/0f8285bc_87da58a3
PS6, Line 3: #include <baseboard/variants.h>
> please remove unused header.
it consumed by variant_updm_update. so keep the header file.
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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/zork/romstage.c:
https://review.coreboot.org/c/coreboot/+/51181/comment/5e3f1839_5734bc2b
PS2, Line 3: #include <baseboard/variants.h>
> it still need used for void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {} […]
I mean <console/console.h> <console/uart.h>..etc.
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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/zork/romstage.c:
https://review.coreboot.org/c/coreboot/+/51181/comment/d3c5b85d_973c11f9
PS2, Line 3: #include <baseboard/variants.h>
> please remove the unused header.
it still need used for void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {}
so keep the header file.
File src/mainboard/google/zork/variants/vilboz/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/51181/comment/e2cf35bc_45be1e36
PS2, Line 5: romstage-y += romstage.c
> this should be in another CL.
Done
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Change subject: mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with wrong date code MB
......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51200/comment/6aa1a37f_f8fb9f62
PS7, Line 10: judement MB
identify build
File src/mainboard/google/volteer/variants/lindar/memory.c:
https://review.coreboot.org/c/coreboot/+/51200/comment/23763586_7cc1c50d
PS6, Line 4: #include <memory_info.h>
Is this required?
https://review.coreboot.org/c/coreboot/+/51200/comment/9e9293e3_d2a8bbef
PS6, Line 5: #include <fw_config.h>
Is this required?
https://review.coreboot.org/c/coreboot/+/51200/comment/245739aa_0b89f7ad
PS6, Line 7: #include <soc/romstage.h>
Is this required?
https://review.coreboot.org/c/coreboot/+/51200/comment/c6cbbe69_29debf18
PS6, Line 72: (google_chromeec_get_board_version(&board_version) == 0) && (board_version == 1
Use board_id() instead because it stashes the board_version once it is read from the EC in a particular stage and avoids multiple calls to the EC.
https://review.coreboot.org/c/coreboot/+/51200/comment/d6f5b289_28132f1b
PS6, Line 73: mem_cfg->SaGv
I usually recommend not touching the UPDs in mainboard. But given that this is a temporary workaround, I think it is okay. Can you please file a separate bug to ensure that this workaround gets dropped once board version 1 is deprecated?
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Change subject: mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with wrong date code MB
......................................................................
Patch Set 7: Code-Review+1
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/dedede/var/sasukette: Add USB2 PHY parameters
......................................................................
mb/google/dedede/var/sasukette: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for sasukette.
BUG=180753635
TEST=Built and verified USB2 eye diagram test result
Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com>
Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146
---
M src/mainboard/google/dedede/variants/sasukette/overridetree.cb
1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/51247/2
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