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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51250
to look at the new patch set (#2).
Change subject: soc/intel/common/block/cpu: Use tab instead of space
......................................................................
soc/intel/common/block/cpu: Use tab instead of space
Convert the lines starts with whitespace with tab as applicable.
Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/51250/2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51251 )
Change subject: soc/intel/common/block/cpu: Update the comments
......................................................................
soc/intel/common/block/cpu: Update the comments
The total LLC size/way size gives the number of ways of LLC.
DCACHE_RAM_SIZE/way size gives the number of data ways that need
to be configured for non-eviction.
Change-Id: Ifcbd577c360a1ebc34cbd4770ef12aad82b4fc71
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/51251/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 4df7eac..1dd901e 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -414,8 +414,8 @@
subl $0x01, %eax
set_eviction_mask:
- mov %ebx, %ecx /* back up number of ways */
- mov %eax, %ebx /* back up the non-eviction mask*/
+ mov %ebx, %ecx /* back up number of ways of LLC */
+ mov %eax, %ebx /* back up the number of data ways */
#if CONFIG(CAR_HAS_SF_MASKS)
mov %ecx, %edi /* use number of ways to prepare SF mask */
/*
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51250 )
Change subject: soc/intel/common/block/cpu: Use tab instead space
......................................................................
soc/intel/common/block/cpu: Use tab instead space
Convert the lines starts with whitespace with tab as applicable.
Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/51250/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 49b40a8..4df7eac 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -398,9 +398,9 @@
* Then we need to allocate just one way for non-eviction
* of RW data.
*/
- movl $0x01, %eax
- cmp $CONFIG_DCACHE_RAM_SIZE, %ecx
- jnc set_eviction_mask
+ movl $0x01, %eax
+ cmp $CONFIG_DCACHE_RAM_SIZE, %ecx
+ jnc set_eviction_mask
/*
* RW data size / way size is equal to number of
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Change subject: mb/google/volteer/variant/copano: Add gpio-keys ACPI node for PENH
......................................................................
Patch Set 1: Code-Review+1
This change is ready for review.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51084 )
Change subject: sb/amd/sb800: Remove unused assignment
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/southbridge/amd/cimx/sb800/bootblock.c:
https://review.coreboot.org/c/coreboot/+/51084/comment/f2731d26_04c3a2f3
PS1, Line 35: pci_s_read_config16(dev, 0x6c);
You drop this line I think.
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