coreboot-gerrit March 2021

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Change in coreboot[master]: soc/mediatek/mt8192: mt6315: update initial setting
by Hung-Te Lin (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Yu-Ping Wu, hsin-hsiung wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51246 ) Change subject: soc/mediatek/mt8192: mt6315: update initial setting ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51246/comment/4aead0fd_88069ba9 PS1, Line 7: update are we updating this to fix a bug or simply revising? https://review.coreboot.org/c/coreboot/+/51246/comment/c53ceb48_46c7be0d PS1, Line 9: According to current flow, we don't check the boot reason of mt6315, so : removing the unused setting about boot status. : Reset power-off sequence to zero to make sure it meets hardware : requirement. - Remove unused boot status settings - Reset the power-off sequence to zero to meet hardware requirement Even better if you can provide more info on what hardware requirement this would help to meet? -- To view, visit https://review.coreboot.org/c/coreboot/+/51246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6 Gerrit-Change-Number: 51246 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 05:28:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: mt6315: update correct slave id
by Hung-Te Lin (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Yu-Ping Wu, hsin-hsiung wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51056 ) Change subject: soc/mediatek/mt8192: mt6315: update correct slave id ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51056/comment/e811709d_3a4fcd63 PS2, Line 9: We found the initial setting of MT6315 is not applied due to : the wrong slave id. : Update correct slave id to fix it. The initial settings for MT6315 was not applied correctly because the setup process didn't specify correct slave id (incorrectly always sending 0). -- To view, visit https://review.coreboot.org/c/coreboot/+/51056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47 Gerrit-Change-Number: 51056 Gerrit-PatchSet: 2 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicolas Boichat <drinkcat(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 05:26:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: mt6315: update initial flow
by Hung-Te Lin (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: hsin-hsiung wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51245 ) Change subject: soc/mediatek/mt8192: mt6315: update initial flow ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51245/comment/049b3033_8391b1bb PS1, Line 9: programming guide please provide the name of that datasheet/guide (just the name would be enough, even better if you can provide which section contains that info) https://review.coreboot.org/c/coreboot/+/51245/comment/3f7968a2_f681b253 PS1, Line 11: Although there is no issue about it, we still want to update it in order : to sync with programming guide. : no need to have this comment :) -- To view, visit https://review.coreboot.org/c/coreboot/+/51245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7 Gerrit-Change-Number: 51245 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 05:24:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: mt6315: update initial setting
by hsin-hsiung wang (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Hung-Te Lin. hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51246 ) Change subject: soc/mediatek/mt8192: mt6315: update initial setting ...................................................................... soc/mediatek/mt8192: mt6315: update initial setting According to current flow, we don't check the boot reason of mt6315, so removing the unused setting about boot status. Reset power-off sequence to zero to make sure it meets hardware requirement. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6 --- M src/soc/mediatek/mt8192/mt6315.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/51246/1 diff --git a/src/soc/mediatek/mt8192/mt6315.c b/src/soc/mediatek/mt8192/mt6315.c index 7f9b770..4f3e54c 100644 --- a/src/soc/mediatek/mt8192/mt6315.c +++ b/src/soc/mediatek/mt8192/mt6315.c @@ -20,11 +20,6 @@ {0x1417, 0x43, 0xFF, 0}, {0x3A2, 0x2A, 0xFF, 0}, {0x3A1, 0x7C, 0xFF, 0}, - /* clear boot status */ - {0x12A, 0x3, 0xFF, 0}, - {0xD, 1, 0x1, 0}, - {0xD, 0, 0x1, 0}, - {0x1416, 0xF, 0xF, 0}, /* init setting */ {0x13, 0x2, 0x2, 0}, {0x15, 0x1F, 0x1F, 0}, @@ -90,6 +85,8 @@ {0x16AC, 0xD7, 0xFF, 0}, {0x16AD, 0x81, 0xFF, 0}, {0x16AE, 0x13, 0x3F, 0}, + /* reset sequence off to zero */ + {0x139, 0, 0x1, 0}, /* enable magic key protection */ {0x3A1, 0, 0xFF, 0}, {0x3A2, 0, 0xFF, 0}, @@ -182,6 +179,8 @@ {0x16AE, 0x13, 0x3F, 0}, /* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */ {0x1440, 0x0, 0x4, 0}, + /* reset sequence off to zero */ + {0x139, 0, 0x1, 0}, /* enable magic key protection */ {0x3A1, 0, 0xFF, 0}, {0x3A2, 0, 0xFF, 0}, -- To view, visit https://review.coreboot.org/c/coreboot/+/51246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6 Gerrit-Change-Number: 51246 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: mt6315: update initial flow
by hsin-hsiung wang (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Hung-Te Lin. hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51245 ) Change subject: soc/mediatek/mt8192: mt6315: update initial flow ...................................................................... soc/mediatek/mt8192: mt6315: update initial flow After checking the programming guide, we found there are something wrong about the sequence of magic key protection flow and clk setting. Although there is no issue about it, we still want to update it in order to sync with programming guide. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7 --- M src/soc/mediatek/mt8192/mt6315.c M src/soc/mediatek/mt8192/pmif_spmi.c 2 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/51245/1 diff --git a/src/soc/mediatek/mt8192/mt6315.c b/src/soc/mediatek/mt8192/mt6315.c index 1cb1fe3..7f9b770 100644 --- a/src/soc/mediatek/mt8192/mt6315.c +++ b/src/soc/mediatek/mt8192/mt6315.c @@ -91,16 +91,16 @@ {0x16AD, 0x81, 0xFF, 0}, {0x16AE, 0x13, 0x3F, 0}, /* enable magic key protection */ - {0x3A9, 0, 0xFF, 0}, - {0x3A8, 0, 0xFF, 0}, - {0x3A0, 0, 0xFF, 0}, - {0x39F, 0, 0xFF, 0}, - {0x993, 0, 0xFF, 0}, - {0x992, 0, 0xFF, 0}, - {0x1418, 0, 0xFF, 0}, + {0x3A1, 0, 0xFF, 0}, + {0x3A2, 0, 0xFF, 0}, {0x1417, 0, 0xFF, 0}, - {0x3a2, 0, 0xFF, 0}, - {0x3a1, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, }; static const struct mt6315_setting init_setting_gpu[] = { @@ -183,16 +183,16 @@ /* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */ {0x1440, 0x0, 0x4, 0}, /* enable magic key protection */ - {0x3A9, 0, 0xFF, 0}, - {0x3A8, 0, 0xFF, 0}, - {0x3A0, 0, 0xFF, 0}, - {0x39F, 0, 0xFF, 0}, - {0x993, 0, 0xFF, 0}, - {0x992, 0, 0xFF, 0}, - {0x1418, 0, 0xFF, 0}, + {0x3A1, 0, 0xFF, 0}, + {0x3A2, 0, 0xFF, 0}, {0x1417, 0, 0xFF, 0}, - {0x3a2, 0, 0xFF, 0}, - {0x3a1, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, }; static void mt6315_read(u32 slvid, u32 reg, u32 *data) @@ -219,8 +219,8 @@ mt6315_write(slvid, 0x127, 0x8); udelay(50); mt6315_write(slvid, 0x128, 0x8); - mt6315_write(slvid, 0x3A9, 0); mt6315_write(slvid, 0x3A8, 0); + mt6315_write(slvid, 0x3A9, 0); } static void mt6315_init_setting(void) diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c index 87b003b..9b710d1 100644 --- a/src/soc/mediatek/mt8192/pmif_spmi.c +++ b/src/soc/mediatek/mt8192/pmif_spmi.c @@ -62,7 +62,7 @@ /* Software reset */ SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x85); - SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15, + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15_clr, CLK_SPMI_MST_SEL, 0x7, CLK_SPMI_MST_INT, 1, PDN_SPMI_MST, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/51245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7 Gerrit-Change-Number: 51245 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: mt6315: update correct slave id
by hsin-hsiung wang (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, hsin-hsiung wang. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51056 to look at the new patch set (#2). Change subject: soc/mediatek/mt8192: mt6315: update correct slave id ...................................................................... soc/mediatek/mt8192: mt6315: update correct slave id We found the initial setting of MT6315 is not applied due to the wrong slave id. Update correct slave id to fix it. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47 --- M src/soc/mediatek/mt8192/mt6315.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/51056/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47 Gerrit-Change-Number: 51056 Gerrit-PatchSet: 2 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicolas Boichat <drinkcat(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add Cr50 support
by Aamir Bohra (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Paul Menzel. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51086 ) Change subject: mb/intel/shadowmountain: Add Cr50 support ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51086/comment/49b31163_15d99ccc PS3, Line 9: Add Cr50 support over GSPI0. > Maybe also mention the GPIO here. Done https://review.coreboot.org/c/coreboot/+/51086/comment/676122f3_e63c8682 PS3, Line 10: > Tested how? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Gerrit-Change-Number: 51086 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Mar 2021 04:41:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add Cr50 support
by Aamir Bohra (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Aamir Bohra. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51086 to look at the new patch set (#4). Change subject: mb/intel/shadowmountain: Add Cr50 support ...................................................................... mb/intel/shadowmountain: Add Cr50 support Add Cr50 support over GSPI0. Also add a 20K internal pull up for H1_TPM_INT_L(GPP_C3). BUG=b:175579964 TEST=Verify TPM init is done in verstage. Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c 4 files changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/51086/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Gerrit-Change-Number: 51086 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/intel/fsp2_0: Allow function to run serially on all APs
by Furquan Shaikh (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51085 ) Change subject: driver/intel/fsp2_0: Allow function to run serially on all APs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Any update here? -- To view, visit https://review.coreboot.org/c/coreboot/+/51085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92 Gerrit-Change-Number: 51085 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Mar 2021 04:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add PCH lockdown
by Rocky Phagura (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Marc Jones, Furquan Shaikh, Martin Roth, Jonathan Zhang, Johnny Lin, Stefan Reinauer, Rocky Phagura, Angel Pons, Michael Niewöhner, Patrick Rudolph. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49849 ) Change subject: soc/intel/xeon_sp: Add PCH lockdown ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/pch/Kconfig: https://review.coreboot.org/c/coreboot/+/49849/comment/6cf3f9a2_3eddd09e PS4, Line 21: if !XEON_SP_COMMON_BASE > We could at least add a SERVER group for this patch. It would make this a little cleaner. […] Grouping would be good but remember that Server platforms will evolve and there will be servers in the future without "PCHs" or other features. As long as we can separate the functionality from these groups easily, then it should be okay. -- To view, visit https://review.coreboot.org/c/coreboot/+/49849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0 Gerrit-Change-Number: 49849 Gerrit-PatchSet: 4 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Mar 2021 04:03:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marc Jones <marc(a)marcjonesconsulting.com> Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2021