coreboot-gerrit February 2021

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Change in coreboot[master]: mb/google/zork: Adjust Dirinboz H1 I2C CLK
by Kevin Chiu (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Kevin Chiu, Martin Roth, Furquan Shaikh, Bhanu Prakash Maiya, Eric Peers. Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Patrick Georgi, Bhanu Prakash Maiya, Eric Peers, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50284 to look at the new patch set (#2). Change subject: mb/google/zork: Adjust Dirinboz H1 I2C CLK ...................................................................... mb/google/zork: Adjust Dirinboz H1 I2C CLK Adjust H1 I2C CLK: 404kHz -> 391 kHz BUG=b:178656936 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/50284/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Gerrit-Change-Number: 50284 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by V Sowmya (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Angel Pons, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 ) Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... Patch Set 6: (1 comment) File src/mainboard/intel/shadowmountain/Kconfig: https://review.coreboot.org/c/coreboot/+/49479/comment/9259112f_45aa0078 PS5, Line 24: default y > Selecting it is even worse: now CHROMEOS can never be disabled... @angel, This should never be disabled for this mainboard and i also verified that disabling it doesn't cause any build error (abuild), any suggestion on handling this since this needs to be enabled? -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 13:04:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: V Sowmya <v.sowmya(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Adjust Dirinboz H1 I2C CLK
by Kevin Chiu (Code Review) 04 Feb '21

04 Feb '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50284 ) Change subject: mb/google/zork: Adjust Dirinboz H1 I2C CLK ...................................................................... mb/google/zork: Adjust Dirinboz H1 I2C CLK Adjust H1 I2C CLK: 404kHz -> 391 kHz BUG=b:164757545 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/50284/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index a990a23..d1c742d 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -90,8 +90,8 @@ # I2C3 for H1 register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 42, /* 1.26v to 0 */ + .rise_time_ns = 98, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 17, /* 1.26v to 0 */ .early_init = true, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/50284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Gerrit-Change-Number: 50284 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update telemetry settings for dirinboz
by Kevin Chiu (Code Review) 04 Feb '21

04 Feb '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50283 ) Change subject: mb/google/zork: update telemetry settings for dirinboz ...................................................................... mb/google/zork: update telemetry settings for dirinboz update telemetry to improve the performance. BUG=b:168585079 BRANCH=zork TEST=1. emerge-zork coreboot 2. run AMD stardust test => pass Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/50283/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 626d281..a990a23 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -15,10 +15,10 @@ register "stapm_time_constant_s" = "1640" register "sustained_power_limit_mW" = "4800" - register "telemetry_vddcr_vdd_slope_mA" = "42465" - register "telemetry_vddcr_vdd_offset" = "69" - register "telemetry_vddcr_soc_slope_mA" = "42667" - register "telemetry_vddcr_soc_offset" = "167" + register "telemetry_vddcr_vdd_slope_mA" = "41322" + register "telemetry_vddcr_vdd_offset" = "-25" + register "telemetry_vddcr_soc_slope_mA" = "43440" + register "telemetry_vddcr_soc_offset" = "115" # End : OPN Performance Configuration # USB 2.0 strength - MB type-C C0 -- To view, visit https://review.coreboot.org/c/coreboot/+/50283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44 Gerrit-Change-Number: 50283 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update USB 3 controller phy Parameter for dirinboz
by Kevin Chiu (Code Review) 04 Feb '21

04 Feb '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50282 ) Change subject: mb/google/zork: update USB 3 controller phy Parameter for dirinboz ...................................................................... mb/google/zork: update USB 3 controller phy Parameter for dirinboz Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:175192931 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50282/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 554cdea..626d281 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -60,6 +60,26 @@ .tx_res_tune = 0x01, }" + # USB3 phy parameter + register "usb3_phy_en" = "1" + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x8, + .rx_eq_delta_iq_ovrd_en = 0x1, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x01" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x01" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/50282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Gerrit-Change-Number: 50282 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/variants/vilboz: Enable BayHub lv2 driver
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49822 ) Change subject: mb/google/zork/variants/vilboz: Enable BayHub lv2 driver ...................................................................... mb/google/zork/variants/vilboz: Enable BayHub lv2 driver Enable this driver along with power saving. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/variants/vilboz/overridetree.cb 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 4fce3b8..fe22650 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -46,6 +46,7 @@ select HAVE_ACPI_RESUME select DRIVERS_USB_ACPI select DRIVERS_UART_ACPI + select DRIVERS_GENERIC_BAYHUB_LV2 config ELOG_BOOT_COUNT_CMOS_OFFSET int diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index ad5cc7e..56b7972 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -75,6 +75,12 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + device pci 1.3 on + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end # GPP Bridge 2 - SD device pci 8.1 on device pci 0.5 on chip drivers/amd/i2s_machine_dev -- To view, visit https://review.coreboot.org/c/coreboot/+/49822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972 Gerrit-Change-Number: 49822 Gerrit-PatchSet: 12 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/generic/bayhub_lv2: Add driver for BayHub lv2
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49783 ) Change subject: drivers/generic/bayhub_lv2: Add driver for BayHub lv2 ...................................................................... drivers/generic/bayhub_lv2: Add driver for BayHub lv2 Add a driver which puts the device into power-saving mode. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/drivers/generic/bayhub_lv2/Kconfig A src/drivers/generic/bayhub_lv2/Makefile.inc A src/drivers/generic/bayhub_lv2/chip.h A src/drivers/generic/bayhub_lv2/lv2.c A src/drivers/generic/bayhub_lv2/lv2.h M src/include/device/pci_ids.h 6 files changed, 124 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/drivers/generic/bayhub_lv2/Kconfig b/src/drivers/generic/bayhub_lv2/Kconfig new file mode 100644 index 0000000..e9f66af --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_BAYHUB_LV2 + bool diff --git a/src/drivers/generic/bayhub_lv2/Makefile.inc b/src/drivers/generic/bayhub_lv2/Makefile.inc new file mode 100644 index 0000000..11249a9 --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_BAYHUB_LV2) += lv2.c diff --git a/src/drivers/generic/bayhub_lv2/chip.h b/src/drivers/generic/bayhub_lv2/chip.h new file mode 100644 index 0000000..aa8f3fd --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdbool.h> + +/* Bayhub LV2 PCIe to SD bridge */ +struct drivers_generic_bayhub_lv2_config { + bool enable_power_saving; +}; diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c new file mode 100644 index 0000000..9e9f074 --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for BayHub Technology LV2 PCI to SD bridge */ + +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include "chip.h" +#include "lv2.h" + +static void lv2_init(struct device *dev) +{ + struct drivers_generic_bayhub_lv2_config *config = dev->chip_info; + pci_dev_init(dev); + + if (!config || !config->enable_power_saving) + return; + /* + * This procedure for enabling power-saving mode is from the + * BayHub BIOS Implementation Guideline document. + */ + pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF); + pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE); + pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER); + pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER); + pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE); + pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING); + pci_update_config32(dev, LV2_PCR_HEX_248, LV2_L1_SUBSTATE_SETTING_MASK, + LV2_L1_SUBSTATE_SETTING); + pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK, + LV2_L1_SUBSTATE_OPTIMISE); + pci_or_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_CLKREQ); + pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW); + pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK, + LV2_DRIVER_STRENGTH); + pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK, + LV2_RESET_DMA_DISABLE); + pci_update_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_L1_L0_MASK, + LV2_LINK_CTRL_L1_ENABLE); + pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON); + printk(BIOS_INFO, "BayHub LV2: Power-saving enabled (link_ctrl=%#x)\n", + pci_read_config32(dev, LV2_LINK_CTRL)); +} + +static struct device_operations lv2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .init = lv2_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_O2_LV2, + 0 +}; + +static const struct pci_driver bayhub_lv2 __pci_driver = { + .ops = &lv2_ops, + .vendor = PCI_VENDOR_ID_O2, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_bayhub_lv2_ops = { + CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge") +}; diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h new file mode 100644 index 0000000..464fed8 --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/lv2.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for BayHub Technology LV2 PCIe to SD bridge */ + +#include <types.h> + +enum { + LV2_PROTECT = 0xD0, + LV2_PROTECT_LOCK_OFF = 0, + LV2_PROTECT_LOCK_ON = BIT(0), + LV2_PROTECT_OFF = 0, + LV2_PROTECT_ON = BIT(31), + LV2_PCR_HEX_FC = 0xFC, + LV2_PCIE_PHY_P1_ENABLE = BIT(25), + LV2_ASPM_L1_TIMER = 0x000E0000, + LV2_ASPM_L1_TIMER_MASK = 0xFFF0FFFF, + LV2_PCR_HEX_A8 = 0xA8, + LV2_LTR_ENABLE = BIT(10), + LV2_PCR_HEX_E0 = 0xE0, + LV2_PCI_PM_L1_TIMER = 0x30000000, + LV2_PCI_PM_L1_TIMER_MASK = 0x0FFFFFFF, + LV2_PCR_HEX_234 = 0x234, + LV2_MAX_LATENCY_SETTING = 0x10011001, + LV2_PCR_HEX_248 = 0x248, + LV2_L1_SUBSTATE_SETTING = 0x0000000A, + LV2_L1_SUBSTATE_SETTING_MASK = 0xFFFFFFF0, + LV2_PCR_HEX_3F4 = 0x3F4, + LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A, + LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0, + LV2_PCR_HEX_300 = 0x300, + LV2_TUNING_WINDOW = 0x00006055, + LV2_TUNING_WINDOW_MASK = 0xFFFF0F00, + LV2_PCR_HEX_304 = 0x304, + LV2_DRIVER_STRENGTH = 0x0000224B, + LV2_DRIVER_STRENGTH_MASK = 0xFFFF0000, + LV2_PCR_HEX_308 = 0x308, + LV2_RESET_DMA_DISABLE = 0x00C00000, + LV2_RESET_DMA_DISABLE_MASK = 0xFF3FFFFF, + LV2_LINK_CTRL = 0x90, + LV2_LINK_CTRL_L1_ENABLE = BIT(1), + LV2_LINK_CTRL_L1_L0_MASK = 0xFFFFFFFC, + LV2_LINK_CTRL_CLKREQ = BIT(8), +}; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 896183f..d6e0ee7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1753,6 +1753,7 @@ #define PCI_DEVICE_ID_O2_6832 0x6832 #define PCI_DEVICE_ID_O2_6836 0x6836 #define PCI_DEVICE_ID_O2_BH720 0x8620 +#define PCI_DEVICE_ID_O2_LV2 0x8621 #define PCI_VENDOR_ID_3DFX 0x121a #define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 -- To view, visit https://review.coreboot.org/c/coreboot/+/49783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc Gerrit-Change-Number: 49783 Gerrit-PatchSet: 10 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: HACK: src/commonlib/fsp_relocate: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 04 Feb '21

04 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48173 ) Change subject: HACK: src/commonlib/fsp_relocate: Fix compilation under x86_64 ...................................................................... HACK: src/commonlib/fsp_relocate: Fix compilation under x86_64 Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/fsp_relocate.c M src/vendorcode/intel/Makefile.inc M src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h 4 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/48173/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 5d326b6..0e5556f 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -12,6 +12,8 @@ /* Default bind FSP 1.1 API to edk2 UEFI 2.4 types. */ #include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> +#define UINTN size_t + #include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> /* Restore original packing policy. */ diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 23ae587..3a8d491 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -6,18 +6,38 @@ # ProcessorBind.h isn't just about types. There's compiler definitions as well # as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for # a fixed width type. +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include else ifeq ($(CONFIG_UDK_2015_BINDING),y) +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include else ifeq ($(CONFIG_UDK_2017_BINDING),y) +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include else ifeq ($(CONFIG_UDK_202005_BINDING),y) +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include endif diff --git a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h index 2f77042..0394e02 100644 --- a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h +++ b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h @@ -275,7 +275,7 @@ /// /// GCC specific method for EFIAPI calling convention. /// - #define EFIAPI __attribute__((cdecl)) + #define EFIAPI #else /// /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h index 69eba65..5d3ed0c 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h @@ -278,11 +278,15 @@ /// #define EFIAPI __cdecl #elif defined(__GNUC__) +#ifndef __x86_64__ /// /// GCC specific method for EFIAPI calling convention. /// #define EFIAPI __attribute__((cdecl)) #else + #define EFIAPI +#endif +#else /// /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI /// is the standard. -- To view, visit https://review.coreboot.org/c/coreboot/+/48173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Gerrit-Change-Number: 48173 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: drivers/intel/fsp2_0: Fix running on x86_64
by Patrick Rudolph (Code Review) 04 Feb '21

04 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48174 ) Change subject: drivers/intel/fsp2_0: Fix running on x86_64 ...................................................................... drivers/intel/fsp2_0: Fix running on x86_64 The FSP info header was using size_t instead of the native data type used to compile the binary. This caused the FSP-M to not being recognized by the loader. Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c 6 files changed, 92 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/48174/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 03b9c2b..4e88795 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -1,5 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only +config PLATFORM_USES_FSP2_X86_32 + bool + default y + help + The FSP 2.0 build runs in x86_32 protected mode. + +config PLATFORM_USES_FSP2_X86_64 + bool + depends on !PLATFORM_USES_FSP2_X86_32 + default y + help + The FSP 2.0 build runs in x86_64 long mode. + config PLATFORM_USES_FSP2_0 bool default n diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f237a37..7f09cc6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -4,6 +4,7 @@ #define _FSP2_0_INFO_HEADER_H_ #include <types.h> +#include <commonlib/bsd/compiler.h> #define FSP_HDR_OFFSET 0x94 #if CONFIG(PLATFORM_USES_FSP2_2) @@ -16,24 +17,46 @@ #define FSP_HDR_ATTRIB_FSPM 2 #define FSP_HDR_ATTRIB_FSPS 3 +#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { uint32_t fsp_revision; - size_t image_size; - uintptr_t image_base; + uint32_t image_size; + uint32_t image_base; uint16_t image_attribute; uint8_t spec_version; uint16_t component_attribute; - size_t cfg_region_offset; - size_t cfg_region_size; - size_t temp_ram_init_entry; - size_t temp_ram_exit_entry; - size_t notify_phase_entry_offset; - size_t memory_init_entry_offset; - size_t silicon_init_entry_offset; - size_t multi_phase_si_init_entry_offset; + uint32_t cfg_region_offset; + uint32_t cfg_region_size; + uint32_t temp_ram_init_entry; + uint32_t temp_ram_exit_entry; + uint32_t notify_phase_entry_offset; + uint32_t memory_init_entry_offset; + uint32_t silicon_init_entry_offset; + uint32_t multi_phase_si_init_entry_offset; char image_id[sizeof(uint64_t) + 1]; uint8_t revision; -}; +} __packed; +#else +struct fsp_header { + uint32_t fsp_revision; + uint64_t image_size; + uint64_t image_base; + uint16_t image_attribute; + uint8_t spec_version; + uint16_t component_attribute; + uint64_t cfg_region_offset; + uint64_t cfg_region_size; + uint64_t temp_ram_init_entry; + uint64_t temp_ram_exit_entry; + uint64_t notify_phase_entry_offset; + uint64_t memory_init_entry_offset; + uint64_t silicon_init_entry_offset; + uint64_t multi_phase_si_init_entry_offset; + char image_id[sizeof(uint64_t) + 1]; + uint8_t revision; +} __packed; +#endif + enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 979cff3..370fcd3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -21,6 +21,7 @@ uint8_t Reserved[23]; } __packed; +#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct FSPM_ARCH_UPD { /// /// Revision of the structure. For FSP v2.0 value is 1. @@ -31,12 +32,12 @@ /// Pointer to the non-volatile storage (NVS) data buffer. /// If it is NULL it indicates the NVS data is not available. /// - void *NvsBufferPtr; + uint32_t NvsBufferPtr; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - void *StackBase; + uint32_t StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. @@ -53,7 +54,40 @@ uint32_t BootMode; uint8_t Reserved1[8]; } __packed; - +#else +struct FSPM_ARCH_UPD { + /// + /// Revision of the structure. For FSP v2.0 value is 1. + /// + uint8_t Revision; + uint8_t Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + uint64_t NvsBufferPtr; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + uint64_t StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + uint32_t StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + uint32_t BootLoaderTolumSize; + /// + /// Current boot mode. + /// + uint32_t BootMode; + uint8_t Reserved1[8]; +} __packed; +#endif struct FSPS_ARCH_UPD { /// /// Revision of the structure. For FSP v2.2 value is 1. diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 27e34fe..d62888e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -101,7 +101,7 @@ return; /* MRC cache found */ - arch_upd->NvsBufferPtr = data; + arch_upd->NvsBufferPtr = (uintptr_t)data; printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size); } @@ -142,7 +142,7 @@ stack_end) != CB_SUCCESS) return CB_ERR; - arch_upd->StackBase = (void *)stack_begin; + arch_upd->StackBase = stack_begin; return CB_SUCCESS; } @@ -237,7 +237,7 @@ fsp_version = fsp_memory_settings_version(hdr); - upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) die_with_post_code(POST_INVALID_VENDOR_BINARY, @@ -291,7 +291,7 @@ post_code(POST_MEM_PREINIT_PREP_END); /* Call FspMemoryInit */ - fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); post_code(POST_FSP_MEMORY_INIT); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index ee04630..73de605 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -15,7 +15,7 @@ if (!fsps_hdr.notify_phase_entry_offset) die("Notify_phase_entry_offset is zero!\n"); - fspnotify = (void *) (fsps_hdr.image_base + + fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); fsp_before_debug_notify(fspnotify, &notify_params); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0b6540e..d180060 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -85,7 +85,7 @@ struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; - supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); + supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) die_with_post_code(POST_INVALID_VENDOR_BINARY, @@ -111,7 +111,7 @@ logo_entry = soc_load_logo(upd); /* Call SiliconInit */ - silicon_init = (void *) (hdr->image_base + + silicon_init = (void *) (uintptr_t)(hdr->image_base + hdr->silicon_init_entry_offset); fsp_debug_before_silicon_init(silicon_init, supd, upd); @@ -139,7 +139,7 @@ return; /* Call MultiPhaseSiInit */ - multi_phase_si_init = (void *) (hdr->image_base + + multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + hdr->multi_phase_si_init_entry_offset); /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Gerrit-Change-Number: 48174 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 29

Change in coreboot[master]: nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50231 ) Change subject: nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>` ...................................................................... nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>` This partially reverts: - Commit 77d3b655ed - Commit 487c1a24f5 - Commit 875c21f491 - Commit c4d1b47ad9 - Commit b96c358751 - Commit 9cbf26d18e It is intentional to use <device/pci_ops.h> whenever one needs to use PCI config access. The bootblock.c files needing I/O config do not need to be an exception to this. Change-Id: Ifba05717dad404a844618815c5347a05e07a3362 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/x4x/bootblock.c 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index e2cabdb..a9a1e8e 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "gm45.h" diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 0bb8ae2..1336582 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "haswell.h" diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index edb9a8d..448d5e4 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "i945.h" diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 02b63a6..6610a3e 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "ironlake.h" diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 92f9aee..1eba744 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index aedcdd9..f15d181 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -2,8 +2,8 @@ #include <arch/bootblock.h> #include <arch/mmio.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "x4x.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/50231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba05717dad404a844618815c5347a05e07a3362 Gerrit-Change-Number: 50231 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021