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Change subject: soc/intel/*: select MP PPI services version
......................................................................
soc/intel/*: select MP PPI services version
Alder Lake FSP is using MP services1 PPI offered by edk2
package. Rest of Platforms uses MP services2 PPI.
Change-Id: I5c1ef6c5dde359b57412854f6e42fa7acbb1172f
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/50226/3
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I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/fsp2_0: Add support for MP services2 PPI
......................................................................
drivers/intel/fsp2_0: Add support for MP services2 PPI
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.
BUG=b:169196864
Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M 3rdparty/blobs
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h
M src/drivers/intel/fsp2_0/ppi/Kconfig
M src/drivers/intel/fsp2_0/ppi/Makefile.inc
A src/drivers/intel/fsp2_0/ppi/mp_service1.c
A src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/include/efi/efi_datatype.h
A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices2.h
10 files changed, 527 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49474/7
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 )
Change subject: mb/intel/shadowmountain: Add bootblock and verstage code
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/intel/shadowmountain/Kconfig:
https://review.coreboot.org/c/coreboot/+/49479/comment/af82084c_2e23d263
PS6, Line 6: select CHROMEOS
> not by default.
@Sowmya, you don't need to select this by default.
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Change subject: mb/intel/shadowmountain: Add bootblock and verstage code
......................................................................
Patch Set 6: Code-Review-1
(2 comments)
Patchset:
PS6:
Selection of CHROMEOS seems unwarranted and should be explained in detail.
File src/mainboard/intel/shadowmountain/Kconfig:
https://review.coreboot.org/c/coreboot/+/49479/comment/0aba4582_3232a7cc
PS5, Line 24: default y
> @angel, This should never be disabled for this mainboard and i also verified that disabling it doesn […]
If that is true, this is the first board that requires CHROMEOS
selected. Can you please explain what makes this board special
wrt. CHROMEOS? What doesn't work as expected without it selected?
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Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50276 )
Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50276/comment/0f8d07a0_809c971d
PS1, Line 7: mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for burnet/esche
> Line too long
Done
https://review.coreboot.org/c/coreboot/+/50276/comment/09a5a080_437ccf17
PS1, Line 13: master
> none
Done
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
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Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode)
ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank)
BUG=b:165768895
TEST=1. emerge-jacuzzi coreboot
2. power on test ok
Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
---
M src/mainboard/google/kukui/sdram_configs.c
1 file changed, 2 insertions(+), 0 deletions(-)
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode)
ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank)
BUG=b:165768895
BRANCH=master
TEST=1. emerge-jacuzzi coreboot
2. power on test ok
Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
---
M src/mainboard/google/kukui/sdram_configs.c
1 file changed, 2 insertions(+), 0 deletions(-)
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