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Change in coreboot[master]: acpi: Add support for reporting CrashLog in BERT table
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49799 ) Change subject: acpi: Add support for reporting CrashLog in BERT table ...................................................................... acpi: Add support for reporting CrashLog in BERT table Crash Data are collected and sent to the OS via the ACPI BERT. BUG=None TEST=Built, and BERT successfully generated in the crashLog flow. Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpi.c M src/arch/x86/acpi_bert_storage.c M src/arch/x86/include/arch/bert_storage.h M src/commonlib/include/commonlib/cbmem_id.h M src/include/acpi/acpi.h M src/include/cper.h M src/soc/intel/common/block/systemagent/memmap.c 7 files changed, 109 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 05ada08..fc13689 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1331,6 +1331,14 @@ return lpi_desc->header.length; } +/* BERT helpers */ +bool __weak acpi_is_boot_error_src_present(void) +{ + return false; +} + +__weak void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length) {} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -1352,6 +1360,7 @@ acpi_tpm2_t *tpm2; acpi_madt_t *madt; acpi_lpit_t *lpit; + acpi_bert_t *bert; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -1573,6 +1582,20 @@ current = acpi_align_current(current); + if (acpi_is_boot_error_src_present()) { + void *region; + size_t size; + printk(BIOS_DEBUG, "ACPI: * BERT\n"); + bert = (acpi_bert_t *) current; + acpi_soc_fill_bert(bert, &region, &size); + acpi_write_bert(bert, (uintptr_t)region, size); + if (bert->header.length >= sizeof(acpi_bert_t)) { + current += bert->header.length; + acpi_add_table(rsdp, bert); + } + current = acpi_align_current(current); + } + printk(BIOS_DEBUG, "current = %lx\n", current); for (dev = all_devices; dev; dev = dev->next) { diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index de56291..ec31917 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -106,6 +106,7 @@ entries = bert_entry_count(status); entry = acpi_hest_generic_data_nth(status, entries); status->data_length += size; + status->raw_data_length += size; if (entry) entry->data_length += size; } @@ -174,6 +175,7 @@ entry->validation_bits |= ACPI_GENERROR_VALID_TIMESTAMP; status->data_length += sizeof(*entry); + status->raw_data_length += sizeof(*entry); bert_bump_entry_count(status); return entry; @@ -186,12 +188,52 @@ return sizeof(cper_proc_generic_error_section_t); else if (!guidcmp(guid, &CPER_SEC_PROC_IA32X64_GUID)) return sizeof(cper_ia32x64_proc_error_section_t); + else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + return sizeof(cper_fw_err_rec_section_t); /* else if ... sizeof(structures not yet defined) */ printk(BIOS_ERR, "Error: Requested size of unrecognized CPER GUID\n"); return 0; } +void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size) +{ + void *cl_data = bert_allocate_storage(cl_size); + if (!cl_data) { + printk(BIOS_ERR, "Error: Crashlog entry (size %lu) would exceed available region\n", + cl_size); + return NULL; + } + + revise_error_sizes(status, cl_size); + + return cl_data; +} + +/* Helper to append an ACPI Generic Error Data Entry per crashlog data */ +acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status) +{ + acpi_hest_generic_data_v300_t *entry; + cper_fw_err_rec_section_t *fw_err; + + entry = bert_append_error_datasection(status, &CPER_SEC_FW_ERR_REC_REF_GUID); + if (!entry) + return NULL; + + status->block_status |= GENERIC_ERR_STS_UNCORRECTABLE_VALID; + status->error_severity = ACPI_GENERROR_SEV_FATAL; + entry->error_severity = ACPI_GENERROR_SEV_FATAL; + + fw_err = section_of_acpientry(fw_err, entry); + + fw_err->record_type = CRASHLOG_RECORD_TYPE; + fw_err->revision = CRASHLOG_FW_ERR_REV; + fw_err->record_id = 0; + guidcpy(&fw_err->record_guid, &FW_ERR_RECORD_ID_CRASHLOG_GUID); + + return entry; +} + /* Append a new ACPI Generic Error Data Entry plus CPER Error Section to an * existing ACPI Generic Error Status Block. The caller is responsible for * the setting the status and entry severity, as well as populating all fields @@ -486,10 +528,14 @@ if (!status) return NULL; + status->raw_data_length = sizeof(*status); + if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) r = bert_append_genproc(status); else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) r = bert_append_ia32x64(status); + if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + r = bert_append_fw_err(status); /* else if other types not implemented */ else r = NULL; diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 060e1a4..0d373e1 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -41,6 +41,9 @@ * +--------------------------------------------------------------------+ */ +#define CRASHLOG_RECORD_TYPE 0x2 +#define CRASHLOG_FW_ERR_REV 0x2 + /* Get implementation-specific reserved area for generating BERT info */ void bert_reserved_region(void **start, size_t *size); @@ -120,6 +123,9 @@ acpi_hest_generic_data_v300_t *bert_append_ia32x64( acpi_generic_error_status_t *status); +void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size); +acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status); + /* Add a new event to the BERT region. An event consists of an ACPI Error * Status Block, a Generic Error Data Entry, and an associated CPER Error * Section. diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index f58d7b1..ae644de 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -4,6 +4,7 @@ #define _CBMEM_ID_H_ #define CBMEM_ID_ACPI 0x41435049 +#define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_GNVS 0x474e5653 #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 @@ -14,6 +15,7 @@ #define CBMEM_ID_CBTABLE_FWD 0x43425443 #define CBMEM_ID_CB_EARLY_DRAM 0x4544524D #define CBMEM_ID_CONSOLE 0x434f4e53 +#define CBMEM_ID_CPU_CRASHLOG 0x4350555f #define CBMEM_ID_COVERAGE 0x47434f56 #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 #define CBMEM_ID_ELOG 0x454c4f47 @@ -31,6 +33,7 @@ #define CBMEM_ID_MMC_STATUS 0x4d4d4353 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 +#define CBMEM_ID_PMC_CRASHLOG 0x504d435f #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 @@ -76,6 +79,7 @@ #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ + { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ @@ -87,6 +91,7 @@ { CBMEM_ID_CB_EARLY_DRAM, "EARLY DRAM USAGE" }, \ { CBMEM_ID_CONSOLE, "CONSOLE " }, \ { CBMEM_ID_COVERAGE, "COVERAGE " }, \ + { CBMEM_ID_CPU_CRASHLOG, "CPU CRASHLOG"}, \ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ { CBMEM_ID_ELOG, "ELOG " }, \ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ @@ -101,6 +106,7 @@ { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ + { CBMEM_ID_PMC_CRASHLOG, "PMC CRASHLOG"}, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ { CBMEM_ID_MTC, "MTC " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index fa24902..058c0d0 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1075,6 +1075,10 @@ void acpi_create_lpit(acpi_lpit_t *lpit); unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); +/* For crashlog. */ +bool acpi_is_boot_error_src_present(void); +void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length); + /* For ACPI S3 support. */ void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); diff --git a/src/include/cper.h b/src/include/cper.h index b6d182e..020ac41 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -370,6 +370,19 @@ u16 tr; } cper_ia32x64_ctx_x64state_t; +#define FW_ERR_RECORD_ID_CRASHLOG_GUID \ + GUID_INIT(0x8f87f311, 0xc998, 0x4d9e, \ + 0xa0, 0xc4, 0x60, 0x65, 0x51, 0x8c, 0x4f, 0x6d) + +/* Firmware Error Record Reference, UEFI v2.8 sec N.2.10 */ +typedef struct cper_fw_err_rec_section { + u8 record_type; + u8 revision; + u8 reserved[6]; + u64 record_id; + guid_t record_guid; +} cper_fw_err_rec_section_t; + static inline cper_timestamp_t cper_timestamp(int precise) { cper_timestamp_t ts; diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 86ca4e1..ce842e8 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -7,6 +7,7 @@ #include <cpu/x86/smm.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> +#include <arch/bert_storage.h> #include <types.h> /* @@ -49,12 +50,22 @@ * +---------------------------+ 0 */ +#define BERT_REGION_MAX_SIZE 0x10000 + void smm_region(uintptr_t *start, size_t *size) { *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } +void bert_reserved_region(void **start, size_t *size) +{ + *start = cbmem_add(CBMEM_ID_ACPI_BERT, BERT_REGION_MAX_SIZE); + *size = BERT_REGION_MAX_SIZE; + + printk(BIOS_DEBUG, "Reserving BERT start %lx, size %lx\n", (uintptr_t)*start, *size); +} + void fill_postcar_frame(struct postcar_frame *pcf) { /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Gerrit-Change-Number: 49799 Gerrit-PatchSet: 10 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: update thermal table for Eldrid
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50111 ) Change subject: mb/google/volteer: update thermal table for Eldrid ...................................................................... mb/google/volteer: update thermal table for Eldrid 1. Add pl4 value 2. Change policies passive with sensor 0 and 1 3. Change granularity value with pl1 and pl2 BUG=b:178768749 TEST=make buildall Signed-off-by: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 13 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 37e0ab9..6760361 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -3,10 +3,12 @@ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 51, + .tdp_pl4 = 71, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 51, + .tdp_pl4 = 105, }" register "tcc_offset" = "5" # TCC of 95 @@ -98,27 +100,27 @@ register "policies.active" = "{[0] = {.target=DPTF_NONE}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,87,5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60.8,6000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,75,SHUTDOWN)" ## Power Limits Control - # 3-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is fixed at 51W, avg over 28-32s interval + # 3-15W PL1 in 200mW increments, avg over 26-34s interval + # PL2 is fixed at 51W, avg over 26-34s interval register "controls.power_limits" = "{ .pl1 = {.min_power = 3000, .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}, + .time_window_min = 26 * MSECS_PER_SEC, + .time_window_max = 34 * MSECS_PER_SEC, + .granularity = 250,}, .pl2 = {.min_power = 51000, .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}}" + .time_window_min = 26 * MSECS_PER_SEC, + .time_window_max = 34 * MSECS_PER_SEC, + .granularity = 250,}}" device generic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/50111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Gerrit-Change-Number: 50111 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: update thermal table for Eldrid
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Keith Short, Tim Wawrzynczak, Nick Vaccaro, Nick Chen. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50111 ) Change subject: mb/google/volteer: update thermal table for Eldrid ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Gerrit-Change-Number: 50111 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Keith Short <keithshort(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 10:20:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Use some board settings from EEPROM
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48807 ) Change subject: mb/prodrive/hermes: Use some board settings from EEPROM ...................................................................... mb/prodrive/hermes: Use some board settings from EEPROM Cache the board settings in memory to avoid having to read them from the EEPROM multiple times. For now, configure the following settings: - DeepSx - USB power in S5 - Power state after G3 Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/mainboard.c 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/48807/1 diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b24dd56..6893eb7 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,6 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen.h> #include <device/device.h> +#include <intelblocks/pmclib.h> +#include <string.h> +#include <types.h> +#include "variants/baseboard/include/eeprom.h" #include "gpio.h" /* FIXME: Example code below */ @@ -65,6 +70,66 @@ gpio_output(GPP_G4, enable); } +static struct eeprom_board_settings board_settings = {0}; + +static bool board_settings_valid = false; + +static void mainboard_init(void *chip_info) +{ + board_settings_valid = get_board_settings_from_eeprom(&board_settings); + + if (!board_settings_valid) + return; + + config_t *config = config_of_soc(); + config->deep_s5_enable_ac = board_settings.deep_sx_enabled; + config->deep_s5_enable_dc = board_settings.deep_sx_enabled; +} + +static void mainboard_final(struct device *dev) +{ + if (!board_settings_valid) + return; + + /* Encoding: 0 -> S0, 1 -> S5 */ + const bool on = !board_settings.power_state_after_g3; + + pmc_soc_set_afterg3_en(on); +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void mainboard_acpi_fill_ssdt(const struct device *dev) +{ + if (!board_settings_valid) + return; + + const unsigned int usb_power_gpios[] = { GPP_G0, GPP_G1, GPP_G2, GPP_G3, GPP_G4 }; + + /* Function pointer to write STXS or CTXS according to EEPROM board setting */ + int (*acpigen_write_soc_gpio_op)(unsigned int gpio_num); + + if (board_settings.usb_powered_in_s5) + acpigen_write_soc_gpio_op = acpigen_soc_set_tx_gpio; + else + acpigen_write_soc_gpio_op = acpigen_soc_clear_tx_gpio; + + acpigen_write_scope("\\_SB"); + { + acpigen_write_method("MPTS", 1); + { + acpigen_write_if_lequal_op_int(ARG0_OP, 5); + { + for (size_t i = 0; i < ARRAY_SIZE(usb_power_gpios); i++) + acpigen_write_soc_gpio_op(usb_power_gpios[i]); + } + acpigen_pop_len(); + } + acpigen_pop_len(); + } + acpigen_pop_len(); +} +#endif + static void mainboard_enable(struct device *dev) { /* FIXME: Do runtime configuration once the board is production ready */ @@ -82,8 +147,15 @@ mb_usb31_fp_pwr_enable(1); mb_usb2_fp1_pwr_enable(1); mb_usb2_fp2_pwr_enable(1); + + dev->ops->final = mainboard_final; + +#if CONFIG(HAVE_ACPI_TABLES) + dev->ops->acpi_fill_ssdt = mainboard_acpi_fill_ssdt; +#endif } struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14 Gerrit-Change-Number: 48807 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/prodrive/hermes: Define board settings in EEPROM
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48806 ) Change subject: mb/prodrive/hermes: Define board settings in EEPROM ...................................................................... mb/prodrive/hermes: Define board settings in EEPROM Hermes has an EEPROM with firmware configuration data. Add definitions to read and verify the `board settings` from the EEPROM. Subsequent commits will hook up these EEPROM settings. Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48806/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index d7ecdec..2bfdd2f 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -2,12 +2,17 @@ #include <device/pci_ops.h> #include <console/console.h> +#include <crc_byte.h> #include <device/smbus_host.h> #include <soc/intel/common/block/smbus/smbuslib.h> +#include <types.h> + #include "variants/baseboard/include/eeprom.h" #define I2C_ADDR_EEPROM 0x57 +#define EEPROM_OFFSET_BOARD_SETTINGS 0x1f00 + /* * Check Signature in EEPROM (M24C32-FMN6TP) * If signature is there we assume that that the content is valid @@ -28,6 +33,27 @@ return 0; } +/* + * Read board settings from the EEPROM and verify their checksum. + * If checksum is valid, we assume the settings are sane as well. + */ +bool get_board_settings_from_eeprom(struct eeprom_board_settings *board_cfg) +{ + if (read_write_config(board_cfg, EEPROM_OFFSET_BOARD_SETTINGS, 0, sizeof(*board_cfg))) { + printk(BIOS_ERR, "CFG EEPROM: Failed to read board settings\n"); + return false; + } + + const uint32_t crc = + CRC(&board_cfg->raw_settings, sizeof(board_cfg->raw_settings), crc32_byte); + + if (crc != board_cfg->signature) { + printk(BIOS_ERR, "CFG EEPROM: Board settings have invalid checksum\n"); + return false; + } + return true; +} + /* Read data from offset and write it to offset in UPD */ bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size) { diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index 95024b6..8abef56 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -18,6 +18,24 @@ .size = member_size(FSP_S_CONFIG, x)} #endif /* ENV_ROMSTAGE */ +__packed struct eeprom_board_settings { + uint32_t signature; + union { + struct { + uint8_t secureboot; + uint8_t primary_video; + uint8_t deep_sx_enabled; + uint8_t wake_on_usb; + uint8_t usb_powered_in_s5; + uint8_t power_state_after_g3; + uint8_t blue_rear_vref; + uint8_t internal_audio_connection; + uint8_t pxe_boot_capability; + }; + uint8_t raw_settings[9]; + }; +}; + typedef struct { size_t offset; size_t size; @@ -25,3 +43,4 @@ bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size); int check_signature(const size_t offset, const uint64_t signature); +bool get_board_settings_from_eeprom(struct eeprom_board_settings *board_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/48806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818 Gerrit-Change-Number: 48806 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/google/kukui: kakadu: update the initial code for BOE LCD
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50215 ) Change subject: mb/google/kukui: kakadu: update the initial code for BOE LCD ...................................................................... mb/google/kukui: kakadu: update the initial code for BOE LCD The latest initial code is from BOE, the vendor. BUG=b:179206650 BRANCH=kukui TEST=Run long time aging test and the BOE LCD shows normally. Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c 1 file changed, 10 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c index ab13735..3c551a2 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -20,7 +20,8 @@ }, .orientation = LB_FB_ORIENTATION_LEFT_UP, .init = { - INIT_DELAY_CMD(24), + INIT_DCS_CMD(0x10), + INIT_DELAY_CMD(34), INIT_DCS_CMD(0xB0, 0x05), INIT_DCS_CMD(0xB1, 0xE5), INIT_DCS_CMD(0xB3, 0x52), @@ -33,9 +34,9 @@ INIT_DCS_CMD(0xBA, 0x87), INIT_DCS_CMD(0xBF, 0x1F), INIT_DCS_CMD(0xC0, 0x0F), - INIT_DCS_CMD(0xC2, 0x0C), + INIT_DCS_CMD(0xC2, 0x0E), INIT_DCS_CMD(0xC3, 0x02), - INIT_DCS_CMD(0xC4, 0x0C), + INIT_DCS_CMD(0xC4, 0x0A), INIT_DCS_CMD(0xC5, 0x02), INIT_DCS_CMD(0xB0, 0x01), INIT_DCS_CMD(0xE0, 0x26), @@ -305,11 +306,16 @@ INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), + INIT_DELAY_CMD(100), INIT_DCS_CMD(0xB0, 0x00), INIT_DCS_CMD(0xB3, 0x08), INIT_DCS_CMD(0xB0, 0x04), INIT_DCS_CMD(0xB8, 0x68), - INIT_DELAY_CMD(150), + INIT_DELAY_CMD(10), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(100), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(50), INIT_END_CMD, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c Gerrit-Change-Number: 50215 Gerrit-PatchSet: 4 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: src: Remove useless comments in "includes" lines
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50186 ) Change subject: src: Remove useless comments in "includes" lines ...................................................................... src: Remove useless comments in "includes" lines Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/arm/include/armv7/arch/mmio.h M src/drivers/intel/dptf/chip.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/raminit.c M src/lib/ramtest.c M src/mainboard/amd/union_station/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/memory.c M src/mainboard/lippert/frontrunner-af/sema.c M src/northbridge/amd/agesa/family14/dimmSpd.c M src/soc/nvidia/tegra124/include/soc/gpio.h M src/southbridge/amd/cimx/sb800/SBPLATFORM.h 11 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index 173a0a3..45868b5 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -7,7 +7,7 @@ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ -#include <arch/cache.h> /* for dmb() */ +#include <arch/cache.h> #include <endian.h> #include <stdint.h> diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index db4c3ae..5408d9e 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -4,7 +4,7 @@ #define _DRIVERS_INTEL_DPTF_CHIP_H_ #include <acpi/acpigen_dptf.h> -#include <timer.h> /* for MSECS_PER_SEC */ +#include <timer.h> #define DPTF_PASSIVE(src, tgt, tmp, prd) \ {.source = DPTF_##src, .target = DPTF_##tgt, .temp = (tmp), .period = (prd)} diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index c452f0b..23eadfa 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -9,7 +9,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/mma.h> -#include <soc/pm.h> /* chip_power_state */ +#include <soc/pm.h> struct romstage_params { uint32_t fsp_version; diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dd08d77..4c468e5 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -8,7 +8,7 @@ #include <cpu/x86/smm.h> #include <fsp/romstage.h> #include <fsp/util.h> -#include <lib.h> /* hexdump */ +#include <lib.h> #include <string.h> #include <timestamp.h> diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 224393f..45178a7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -1,5 +1,5 @@ #include <stdint.h> -#include <lib.h> /* Prototypes */ +#include <lib.h> #include <console/console.h> #include <device/mmio.h> diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 88ba111..4b6f9a1 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -3,7 +3,7 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 8664560..d3d81fd 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -2,7 +2,7 @@ #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> /* src/include/gpio.h */ +#include <gpio.h> #include <spd_bin.h> #include <variant/gpio.h> #include <amdblocks/dimm_spd.h> diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index fb8e6ef..e80cc12 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <delay.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ +#include <OEM.h> #include <Porting.h> #include <AGESA.h> diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 3ce84a4..d43e6a1 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -2,7 +2,7 @@ #include <device/pci_def.h> #include <device/device.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ +#include <OEM.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> diff --git a/src/soc/nvidia/tegra124/include/soc/gpio.h b/src/soc/nvidia/tegra124/include/soc/gpio.h index 6b66a98..48601dd 100644 --- a/src/soc/nvidia/tegra124/include/soc/gpio.h +++ b/src/soc/nvidia/tegra124/include/soc/gpio.h @@ -4,7 +4,7 @@ #define __SOC_NVIDIA_TEGRA124_GPIO_H__ #include <soc/nvidia/tegra/gpio.h> -#include <soc/pinmux.h> /* for pinmux constants in GPIO macro */ +#include <soc/pinmux.h> /* GPIO index constants. */ diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 99c7323..7600886 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -44,8 +44,8 @@ #include <SBDEF.h> #include <AMDSBLIB.h> #include <SBSUBFUN.h> -#include "platform_cfg.h" /* mainboard specific configuration */ -#include <OEM.h> /* platform default configuration */ +#include "platform_cfg.h" +#include <OEM.h> #include <AMD.h> //------------------------------------------------------------------------------------------------------------------------// -- To view, visit https://review.coreboot.org/c/coreboot/+/50186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Gerrit-Change-Number: 50186 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: memory_info.h: Store SMBIOS error correction type
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Christian Walter, Angel Pons, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, Christian Walter, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50178 to look at the new patch set (#2). Change subject: memory_info.h: Store SMBIOS error correction type ...................................................................... memory_info.h: Store SMBIOS error correction type There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/memory_info.h M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit.c M src/soc/intel/common/block/systemagent/systemagent.c 5 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/50178/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Gerrit-Change-Number: 50178 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/ocp/deltalake: Override mainboard board type
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Christian Walter, Arthur Heymans, Morgan Jang, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50181 ) Change subject: mb/ocp/deltalake: Override mainboard board type ...................................................................... Patch Set 1: (1 comment) File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/50181/comment/186c5c80_deb1d1a2 PS1, Line 62: return SMBIOS_BOARD_TYPE_SERVER_BLADE; > If it should be blade server I can abandon my patch. Since a yv3 chassis can house up to 4 Delta Lake boards, I'd say Delta Lake is a server blade. However, I'm happy to use another board type if necessary/desired. -- To view, visit https://review.coreboot.org/c/coreboot/+/50181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06bde40db69b20962f90b63f3e7be66c950e4d3d Gerrit-Change-Number: 50181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 10:05:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smbios_defaults.c: Default to motherboard type
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Felix Singer, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50180 ) Change subject: arch/x86/smbios_defaults.c: Default to motherboard type ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50180/comment/5315fdbf_7b4c089a PS1, Line 9: Nearly every board that coreboot supports is a motherboard. The only board that currently overrides the function to return a different value is scaleway/tagada (SMBIOS_BOARD_TYPE_SERVER_BLADE), and is not affected by this patch. File src/arch/x86/smbios_defaults.c: https://review.coreboot.org/c/coreboot/+/50180/comment/63407731_3d706794 PS1, Line 63: return SMBIOS_BOARD_TYPE_MOTHERBOARD; > Why? What's the improvement? It's to avoid having to override this for each and every motherboard (see CB:48850 for an example). I doubt this change would have any noticeable impact out of coreboot (e.g. at OS level). -- To view, visit https://review.coreboot.org/c/coreboot/+/50180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1419874a0ba3f2e21568fa4b07b88f2048d10203 Gerrit-Change-Number: 50180 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 10:02:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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coreboot-gerrit February 2021