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Change in coreboot[master]: Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Chang...
by John Su (Code Review) 04 Feb '21

04 Feb '21

John Su has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50279 ) Change subject: Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 Gerrit-Change-Number: 50279 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Chang...
by build bot (Jenkins) (Code Review) 04 Feb '21

04 Feb '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50279 ) Change subject: Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 ...................................................................... Patch Set 1: (81 comments) File src/mainboard/google/zork/variants/vilboz/variant.c: https://review.coreboot.org/c/coreboot/+/50279/comment/6ff20e16_98c5352f PS1, Line 27: { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/a237319a_f63b0e00 PS1, Line 27: { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/e5f062ad_19f63913 PS1, Line 28: // NVME SSD code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/b919139a_bbc0c3cd PS1, Line 29: .port_present = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/71697c0a_0be00a8e PS1, Line 29: .port_present = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/82119474_298c5acc PS1, Line 30: .engine_type = PCIE_ENGINE, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/bca4c0b8_67b060df PS1, Line 30: .engine_type = PCIE_ENGINE, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/edfeda7e_a6bf2164 PS1, Line 31: .start_logical_lane = 4, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/18308345_d792b6fd PS1, Line 31: .start_logical_lane = 4, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/f6785db1_845a2796 PS1, Line 32: .end_logical_lane = 5, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/dfd3a603_42641a74 PS1, Line 32: .end_logical_lane = 5, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/7b0b9f29_99634ad3 PS1, Line 33: .device_number = 1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/445c655e_a92baf95 PS1, Line 33: .device_number = 1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/e0f7a44d_2d4a827f PS1, Line 34: .function_number = 7, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/fb1f4aad_65ebfff1 PS1, Line 34: .function_number = 7, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/b51405a3_a8dc5345 PS1, Line 35: .link_aspm = ASPM_L1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/08202edc_3c3d8674 PS1, Line 35: .link_aspm = ASPM_L1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/ed6e7848_e5d4d17e PS1, Line 36: .link_aspm_L1_1 = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/e1da577b_a88c3916 PS1, Line 36: .link_aspm_L1_1 = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/5a280bf3_d513ae1a PS1, Line 37: .link_aspm_L1_2 = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/69d5f943_0bcc7d08 PS1, Line 37: .link_aspm_L1_2 = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/e5e0030c_8c4c6b1c PS1, Line 38: .turn_off_unused_lanes = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/71ba591c_a4f406e9 PS1, Line 38: .turn_off_unused_lanes = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/eebdd3a3_27bbbb68 PS1, Line 39: .clk_req = CLK_REQ2, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/fafe16dd_565b10f0 PS1, Line 39: .clk_req = CLK_REQ2, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/674e0c1c_8899e998 PS1, Line 40: }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/08a37a9d_b2f88d74 PS1, Line 40: }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/8e4aae6c_6e490c79 PS1, Line 41: { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/6bce6192_fa5430ea PS1, Line 41: { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/a42eca5a_9c6e29db PS1, Line 42: // WLAN code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/fb5cec54_72801d2f PS1, Line 43: .port_present = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/00e67304_6d0fef8d PS1, Line 43: .port_present = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/a7aa5ddf_7fc3cad5 PS1, Line 44: .engine_type = PCIE_ENGINE, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/48347cf4_6ad498f9 PS1, Line 44: .engine_type = PCIE_ENGINE, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/26ef1267_c00080a6 PS1, Line 45: .start_logical_lane = 0, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/9694145d_3f28dc06 PS1, Line 45: .start_logical_lane = 0, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/ae248c0c_059ffeb4 PS1, Line 46: .end_logical_lane = 0, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/d396a3b7_47cf9b69 PS1, Line 46: .end_logical_lane = 0, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/03265419_79b99db2 PS1, Line 47: .device_number = 1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/f3fb6866_416595f8 PS1, Line 47: .device_number = 1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/1df14fd4_9fc31e6e PS1, Line 48: .function_number = 2, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/8633867a_91e41f0a PS1, Line 48: .function_number = 2, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/f4ac6345_a4a802eb PS1, Line 49: .link_aspm = ASPM_L1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/6e747fc0_a73ea8ed PS1, Line 49: .link_aspm = ASPM_L1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/ad25b31e_e5400061 PS1, Line 50: .link_aspm_L1_1 = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/559c5202_67710572 PS1, Line 50: .link_aspm_L1_1 = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/88661b2b_bfe2f4c3 PS1, Line 51: .link_aspm_L1_2 = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/9a158d93_39557e18 PS1, Line 51: .link_aspm_L1_2 = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/2afe9942_77bca55a PS1, Line 52: .turn_off_unused_lanes = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/5cbf2ed9_726a2bb4 PS1, Line 52: .turn_off_unused_lanes = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/db53d7e6_d6ff14ab PS1, Line 53: .clk_req = CLK_REQ0, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/395216b4_537de5e3 PS1, Line 53: .clk_req = CLK_REQ0, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/2ee6d2b4_a4ce252a PS1, Line 54: }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/9d6ddc2e_5d61db6d PS1, Line 54: }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/d3e8df65_025656a6 PS1, Line 55: { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/6379053c_f1ebe504 PS1, Line 55: { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/fdf7f66f_f2b26ee6 PS1, Line 56: // SD Reader code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/e17840aa_3572465b PS1, Line 57: .port_present = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/09a0e998_4539eef7 PS1, Line 57: .port_present = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/100bc13c_a7208eb0 PS1, Line 58: .engine_type = PCIE_ENGINE, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/b10b9b24_0c0ea381 PS1, Line 58: .engine_type = PCIE_ENGINE, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/826fe378_026e90dc PS1, Line 59: .start_logical_lane = 1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/4abb9607_02798e49 PS1, Line 59: .start_logical_lane = 1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/8aae720d_918bee61 PS1, Line 60: .end_logical_lane = 1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/e4715eff_cd62623d PS1, Line 60: .end_logical_lane = 1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/4eb1a55d_90d5dda2 PS1, Line 61: .device_number = 1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/01f44204_202e26eb PS1, Line 61: .device_number = 1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/9d6c7bce_5a5e7a1f PS1, Line 62: .function_number = 3, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/5625a937_7f9c532e PS1, Line 62: .function_number = 3, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/520418b5_382f6a12 PS1, Line 63: .link_aspm = ASPM_L1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/8cf9cb62_6439703d PS1, Line 63: .link_aspm = ASPM_L1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/8a437b6d_043676fb PS1, Line 64: .link_aspm_L1_1 = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/772f7b10_d75c39e2 PS1, Line 64: .link_aspm_L1_1 = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/7f0a49d1_7bb39191 PS1, Line 65: .link_aspm_L1_2 = false, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/ba503959_2fd54fee PS1, Line 65: .link_aspm_L1_2 = false, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/f444cba4_9556b6fa PS1, Line 66: .turn_off_unused_lanes = true, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/fa54d009_2a3f0014 PS1, Line 66: .turn_off_unused_lanes = true, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/a9a384b3_01e1f326 PS1, Line 67: .clk_req = CLK_REQ1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/01a1c74e_c12024ff PS1, Line 67: .clk_req = CLK_REQ1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50279/comment/0008bf28_45151ce9 PS1, Line 68: } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50279/comment/ef5c0fc7_6ff37345 PS1, Line 68: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/50279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 Gerrit-Change-Number: 50279 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 08:48:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/variants/vilboz: Diasable ASPM L1.2 for SD card reader
by John Su (Code Review) 04 Feb '21

04 Feb '21

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50280 ) Change subject: mb/google/zork/variants/vilboz: Diasable ASPM L1.2 for SD card reader ...................................................................... mb/google/zork/variants/vilboz: Diasable ASPM L1.2 for SD card reader From bayhub vendor feedback, OZ711LV2 only set to L1.1 for AMD project, because the reason is AMD’s L1.2 capability is not good causing device lost in past experience,so vilboz need set L1.1 in RC and device both side. BUG=b:177955523 BRANCH=zork TEST=check PCIE_L1_PM_SUB_CNTL 0x378[3:0]=0xA Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50280/1 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index eb49c47..8a3ed7c 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -24,48 +24,48 @@ }; static const fsp_dxio_descriptor vilboz_dxio_descriptors[] = { - { - // NVME SSD - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 4, - .end_logical_lane = 5, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - }, - { - // WLAN - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - }, - { - // SD Reader - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = false, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - } + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = false, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } }; void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, -- To view, visit https://review.coreboot.org/c/coreboot/+/50280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 Gerrit-Change-Number: 50280 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Chang...
by John Su (Code Review) 04 Feb '21

04 Feb '21

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50279 ) Change subject: Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 ...................................................................... Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/50279/1 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 3816aac..eb49c47 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -23,12 +23,58 @@ } }; +static const fsp_dxio_descriptor vilboz_dxio_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = false, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } +}; + void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *dxio_descs = vilboz_dxio_descriptors; + *dxio_num = ARRAY_SIZE(vilboz_dxio_descriptors); *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); -- To view, visit https://review.coreboot.org/c/coreboot/+/50279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33 Gerrit-Change-Number: 50279 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot_table: Move VBOOT_VBNV support
by Kyösti Mälkki (Code Review) 04 Feb '21

04 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50250 ) Change subject: coreboot_table: Move VBOOT_VBNV support ...................................................................... coreboot_table: Move VBOOT_VBNV support The guard changes from (CHROMEOS && PC80_SYSTEM) to VBOOT_VBNV_CMOS here. Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50250 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/security/vboot/vbnv_cmos.c 3 files changed, 17 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 7fd9ac1..e77c60a 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -41,4 +41,7 @@ struct lb_record *lb_new_record(struct lb_header *header); +/* Add VBOOT VBNV offsets. */ +void lb_table_add_vbnv_cmos(struct lb_header *header); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 00d73a0..5f8c69b 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -20,7 +20,6 @@ #include <bootmem.h> #include <bootsplash.h> #include <spi_flash.h> -#include <security/vboot/vbnv_layout.h> #include <smmstore.h> #if CONFIG(USE_OPTION_TABLE) @@ -189,17 +188,6 @@ } } -static void lb_vbnv(struct lb_header *header) -{ - struct lb_range *vbnv; - - vbnv = (struct lb_range *)lb_new_record(header); - vbnv->tag = LB_TAG_VBNV; - vbnv->size = sizeof(*vbnv); - vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; - vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; -} - __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } @@ -487,8 +475,8 @@ lb_gpios(head); /* pass along VBNV offsets in CMOS */ - if (CONFIG(CHROMEOS) && CONFIG(PC80_SYSTEM)) - lb_vbnv(head); + if (CONFIG(VBOOT_VBNV_CMOS)) + lb_table_add_vbnv_cmos(head); /* Pass mmc early init status */ lb_mmc_info(head); diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index a719bb1..35e4c41 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <types.h> #include <pc80/mc146818rtc.h> @@ -86,6 +87,17 @@ } } +void lb_table_add_vbnv_cmos(struct lb_header *header) +{ + struct lb_range *vbnv; + + vbnv = (struct lb_range *)lb_new_record(header); + vbnv->tag = LB_TAG_VBNV; + vbnv->size = sizeof(*vbnv); + vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; + vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; +} + #if CONFIG(VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) static void back_up_vbnv_cmos(void *unused) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187 Gerrit-Change-Number: 50250 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8192: Use LZ4 compression for MCUs
by Yu-Ping Wu (Code Review) 04 Feb '21

04 Feb '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50278 ) Change subject: soc/mediatek/mt8192: Use LZ4 compression for MCUs ...................................................................... soc/mediatek/mt8192: Use LZ4 compression for MCUs For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot process. The loading (plus decompression) time of mcupm.bin and sspm.bin is consistently reduced by 8ms, respectively. BUG=b:177389446 TEST=emerge-asurada coreboot TEST=Hayato booted up BRANCH=none Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/50278/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 9d22ef2..9109e61 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -78,7 +78,7 @@ $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8192_BLOB_DIR)/$(fw)) \ $(eval $(fw)-type := raw) \ - $(eval $(fw)-compression := $(CBFS_COMPRESS_FLAG)) \ + $(eval $(fw)-compression := LZ4) \ $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ ) -- To view, visit https://review.coreboot.org/c/coreboot/+/50278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44 Gerrit-Change-Number: 50278 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/shuboz: Adjust GPIO settings
by Kane Chen (Code Review) 04 Feb '21

04 Feb '21

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50277 ) Change subject: mb/google/zork/var/shuboz: Adjust GPIO settings ...................................................................... mb/google/zork/var/shuboz: Adjust GPIO settings 1. GPIO_4 to NC 2. GPIO_86 to NONE BUG=b: BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b --- M src/mainboard/google/zork/variants/shuboz/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/50277/1 diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c index db20e44..535e91b 100644 --- a/src/mainboard/google/zork/variants/shuboz/gpio.c +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -7,8 +7,12 @@ #include <ec/google/chromeec/ec.h> static const struct soc_amd_gpio bid_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), /* AGPIO_5 - NC */ PAD_NC(GPIO_5), + /* RAM ID 2 */ + PAD_GPI(GPIO_86, PULL_NONE), /* EGPIO141 - NC */ PAD_NC(GPIO_141), /* EGPIO144 - NC (etk5515 not used) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b Gerrit-Change-Number: 50277 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for b...
by Yu-Ping Wu (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Hung-Te Lin, Kevin Chiu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50276 ) Change subject: mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for burnet/esche ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50276/comment/c1cd5285_7a411180 PS1, Line 7: mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for burnet/esche Line too long https://review.coreboot.org/c/coreboot/+/50276/comment/57222d68_c4e75003 PS1, Line 13: master none -- To view, visit https://review.coreboot.org/c/coreboot/+/50276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Gerrit-Change-Number: 50276 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 08:11:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: set USB_PD port0 to USB3.1 mode(flip)
by chris wang (Code Review) 04 Feb '21

04 Feb '21

chris wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49933 ) Change subject: mb/google/zork: set USB_PD port0 to USB3.1 mode(flip) ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13629763690c4cb40a1c917ca2c628332b2de916 Gerrit-Change-Number: 49933 Gerrit-PatchSet: 4 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for b...
by Kevin Chiu (Code Review) 04 Feb '21

04 Feb '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50276 ) Change subject: mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for burnet/esche ...................................................................... mb/google/kukui: Add LPDDR4X byte mode/single rank DRAM support for burnet/esche ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode) ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank) BUG=b:165768895 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/kukui/sdram_configs.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/50276/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index f00bec8..d0b5245 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -30,7 +30,9 @@ [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x15] = "sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB", [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + [0x17] = "sdram-lpddr4x-MT53E1G32D2NP-046-4GB", /* Table shared by Kakadu and its variants, offset = 0x20 */ [0x20] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", -- To view, visit https://review.coreboot.org/c/coreboot/+/50276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Gerrit-Change-Number: 50276 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021