coreboot-gerrit February 2021

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Change in coreboot[master]: mb/google/volteer: Change cTDP level to level 2 (15W)
by Derek Huang (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Nick Vaccaro, Derek Huang, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50105 to look at the new patch set (#3). Change subject: mb/google/volteer: Change cTDP level to level 2 (15W) ...................................................................... mb/google/volteer: Change cTDP level to level 2 (15W) Change the cTDP level from base (28W) to level 2 (15W) to align with PL1. The change is for UP3 variants, UP4 variants should keep base TDP level (9W) which already align with PL1. Refer to Tigerlake TDP specifications (doc #575683, table 4-2) for details BUG=b:179283734 TEST=build and boot system, check MSR 0x64B, bit 1:0 should be 2 Change-Id: I4420a6a2e463b0a6bd7eb4b81f6a4fb975895ea3 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/drobit/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/soc/intel/tigerlake/romstage/fsp_params.c 8 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50105/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4420a6a2e463b0a6bd7eb4b81f6a4fb975895ea3 Gerrit-Change-Number: 50105 Gerrit-PatchSet: 3 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {src}: Assign values before if statement
by Frans Hendriks (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Julius Werner, Kyösti Mälkki, Alexander Couzens, Aaron Durbin, Patrick Rudolph. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50040 ) Change subject: {src}: Assign values before if statement ...................................................................... Patch Set 3: (2 comments) Patchset: PS2: > You most likely will be requested to split all that x86emu whitespace change to different commit. During update something went wrong. This patch should be placed on CB:50123 Patchset: PS3: > This isn't actually a requirement of our Coding Style, and I would vote against making it one. […] I was not aware of history of checkpatch. Goal is cleaning checkpatch output. Disabling ASSIGN_IN_IF is a 'solution, but having a consistent code style is another way of solving this issue. The 'issue' occures in a few files only! -- To view, visit https://review.coreboot.org/c/coreboot/+/50040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd346d31f1da71271ad1545e5645e57530c7b374 Gerrit-Change-Number: 50040 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 07:17:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device: correct code style
by Frans Hendriks (Code Review) 04 Feb '21

04 Feb '21

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49963 ) Change subject: device: correct code style ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49963/comment/35fb3585_b0b2bcc9 PS1, Line 9: lint report errors and warnings : : Solve the next issues: : - BRACES : - EMBEDDED_FUNCTION_NAME : - MULTILINE_DEREFERNCE : - POINTER_LOCATION : - UNNECSSARY_ELSE > I would rephrase the commit body as follows: […] Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/49963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Gerrit-Change-Number: 49963 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Feb 2021 07:16:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
by Furquan Shaikh (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, Andrey Petrov, Patrick Rudolph. Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50275 ) Change subject: intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI ...................................................................... intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h M src/drivers/intel/fsp2_0/ppi/Kconfig M src/drivers/intel/fsp2_0/ppi/Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 10 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/50275/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d054cfe..67a76a1 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -334,7 +334,7 @@ * function will always getting called from coreboot context * (ESP stack pointer will always refer to coreboot). * - * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * But with MP_SERVICES_PPI implementation in coreboot this * assumption might not be true, where FSP context (stack pointer refers * to FSP) will request to get cpu_index(). * diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b622465..c2cc4ef 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -306,7 +306,7 @@ * function will always getting called from coreboot context * (ESP stack pointer will always refer to coreboot). * - * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * But with MP_SERVICES_PPI implementation in coreboot this * assumption might not be true, where FSP context (stack pointer refers * to FSP) will request to get cpu_index(). * diff --git a/src/drivers/intel/fsp2_0/ppi/Kconfig b/src/drivers/intel/fsp2_0/ppi/Kconfig index 4f77a32..bb99dc3 100644 --- a/src/drivers/intel/fsp2_0/ppi/Kconfig +++ b/src/drivers/intel/fsp2_0/ppi/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -config FSP_USES_MP_SERVICES_PPI +config MP_SERVICES_PPI bool default n depends on SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc index 8d8d990..59a550f 100644 --- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc +++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c +ramstage-$(CONFIG_MP_SERVICES_PPI) += mp_service_ppi.c diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0474750..91a3f65 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -34,12 +34,12 @@ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select INTEL_TME + select MP_SERVICES_PPI select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index f4249c6..b1c5aa2 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -75,7 +75,7 @@ config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" - default y if FSP_USES_MP_SERVICES_PPI + default y if MP_SERVICES_PPI default n help This option allows FSP to make use of MP services PPI published by diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 3492640..8c0b4e6 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -26,12 +26,12 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index dc62b10..7915bdb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -26,12 +26,12 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 633a19c..81503c3 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -27,12 +27,12 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 16efca8..6ffde92 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -30,12 +30,12 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM -- To view, visit https://review.coreboot.org/c/coreboot/+/50275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Gerrit-Change-Number: 50275 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel: Drop FSP_PEIM_TO_PEIM_INTERFACE
by Furquan Shaikh (Code Review) 04 Feb '21

04 Feb '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50274 ) Change subject: intel: Drop FSP_PEIM_TO_PEIM_INTERFACE ...................................................................... intel: Drop FSP_PEIM_TO_PEIM_INTERFACE This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 7 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/50274/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 14d9742..0d25630 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -173,16 +173,6 @@ This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory. -config FSP_PEIM_TO_PEIM_INTERFACE - bool - select FSP_USES_MP_SERVICES_PPI - help - This option allows SOC user to create specific PPI for Intel FSP - usage, coreboot will provide required PPI structure definitions - along with all APIs as per EFI specification. So far this feature - is limited till EFI_PEI_MP_SERVICE_PPI and this option might be - useful to add further PPI if required. - config HAVE_FSP_LOGO_SUPPORT bool default n @@ -272,8 +262,6 @@ will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required. -if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" -endif endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b518bec..0943080 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -95,7 +95,6 @@ CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) endif -# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable -subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi +subdirs-y += ppi endif diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 806c91b..0474750 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -39,7 +39,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 2b630d0..f4249c6 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -75,8 +75,7 @@ config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" - depends on FSP_USES_MP_SERVICES_PPI - default y if FSP_PEIM_TO_PEIM_INTERFACE + default y if FSP_USES_MP_SERVICES_PPI default n help This option allows FSP to make use of MP services PPI published by diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7ad103d..3492640 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -31,7 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a14be36..dc62b10 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,7 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 5324d84..633a19c 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -32,7 +32,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cd84bdf..16efca8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -35,7 +35,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM -- To view, visit https://review.coreboot.org/c/coreboot/+/50274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Gerrit-Change-Number: 50274 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/google: cbmem_add_vpd_calibration()
by Kyösti Mälkki (Code Review) 04 Feb '21

04 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48785 ) Change subject: [WIP] mb/google: cbmem_add_vpd_calibration() ...................................................................... [WIP] mb/google: cbmem_add_vpd_calibration() Change-Id: Ica8691e3dc4feecbeb11ba3f5868932f926965b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/gale/mainboard.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/storm/mainboard.c 3 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48785/1 diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index cd55c93..28b5f96 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -31,10 +31,9 @@ setup_mmu(DRAM_INITIALIZED); setup_usb(); - if (CONFIG(CHROMEOS)) { - /* Copy WIFI calibration data into CBMEM. */ + /* Copy WIFI calibration data into CBMEM. */ + if (CONFIG(CHROMEOS)) cbmem_add_vpd_calibration_data(); - } /* * Make sure bootloader can issue sounds The frequency is calculated diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e0cd75d..4079182 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -19,10 +19,9 @@ static void mainboard_init(struct device *dev) { - if (CONFIG(CHROMEOS)) { - /* Copy WIFI calibration data into CBMEM. */ + /* Copy WIFI calibration data into CBMEM. */ + if (CONFIG(CHROMEOS)) cbmem_add_vpd_calibration_data(); - } setup_usb(); } diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 6a89be0..4faf832 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -76,10 +76,9 @@ /* Functionally a 0-cost no-op if NAND is not present */ board_nand_init(); -#if CONFIG(CHROMEOS) /* Copy WIFI calibration data into CBMEM. */ - cbmem_add_vpd_calibration_data(); -#endif + if (CONFIG(CHROMEOS)) + cbmem_add_vpd_calibration_data(); /* * Make sure bootloader can issue sounds The frequency is calculated -- To view, visit https://review.coreboot.org/c/coreboot/+/48785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica8691e3dc4feecbeb11ba3f5868932f926965b2 Gerrit-Change-Number: 48785 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mainboards: Remove default CHROMEOS=y
by Kyösti Mälkki (Code Review) 04 Feb '21

04 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50118 ) Change subject: mainboards: Remove default CHROMEOS=y ...................................................................... mainboards: Remove default CHROMEOS=y Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/tglrvp/Kconfig 13 files changed, 0 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b691cd1..ca76078 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -22,8 +22,6 @@ select SYSTEM_TYPE_LAPTOP config CHROMEOS - bool - default y select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 6928002..466a672 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -38,8 +38,6 @@ select SYSTEM_TYPE_LAPTOP config CHROMEOS - bool - default y select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 8d95849..d351d85 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -22,8 +22,6 @@ if BOARD_GOOGLE_BASEBOARD_DELTAUR config CHROMEOS - bool - default y select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 7470107..311f3f6 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -28,8 +28,6 @@ if BOARD_GOOGLE_BASEBOARD_DRALLION config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d088341..1c10522 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -45,8 +45,6 @@ if BOARD_GOOGLE_HATCH_COMMON config CHROMEOS - bool - default y select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 7e8e277..ba01fe3 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -43,8 +43,6 @@ select SYSTEM_TYPE_LAPTOP config CHROMEOS - bool - default y select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 444234a..9893acf 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -31,8 +31,6 @@ if BOARD_GOOGLE_BASEBOARD_SARIEN config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 3217d07..f4d121e 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -38,8 +38,6 @@ if BOARD_GOOGLE_BASEBOARD_VOLTEER config CHROMEOS - bool - default y select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 35224a1..80d5254 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -18,8 +18,6 @@ select PCIEXP_HOTPLUG config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 0f8075b..e4c2d90 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -44,9 +44,6 @@ default "Intel_cflrvp" config CHROMEOS - bool - default n if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 - default y select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAX_CPUS diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 172dfa2..7fda90d 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -38,8 +38,6 @@ endchoice config CHROMEOS - bool - default y select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH if GLK_CHROME_EC diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 7bfd158..8dec42a 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -51,8 +51,6 @@ default 512 config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 9df542d..233706d 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -26,8 +26,6 @@ select SPI_TPM config CHROMEOS - bool - default y select EC_GOOGLE_CHROMEEC_SWITCHES if TGL_CHROME_EC select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/50118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Gerrit-Change-Number: 50118 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: vc/google/chromeos: Drop <acpi/vpd.asl>
by Kyösti Mälkki (Code Review) 04 Feb '21

04 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49902 ) Change subject: vc/google/chromeos: Drop <acpi/vpd.asl> ...................................................................... vc/google/chromeos: Drop <acpi/vpd.asl> This was used as a means to read the MAC address and dynamically return it to the ethernet driver via ACPI. The kernel team ended up going another direction so this became obsolete. Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/sarien/dsdt.asl D src/vendorcode/google/chromeos/acpi/vpd.asl 4 files changed, 0 insertions(+), 225 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 47758d4..7a74843 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -30,9 +30,6 @@ } } - /* VPD support */ - #include <vendorcode/google/chromeos/acpi/vpd.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2de104e..5556c98 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -31,11 +31,6 @@ #include <variant/acpi/mainboard.asl> } -#if CONFIG(CHROMEOS) - /* VPD support */ - #include <vendorcode/google/chromeos/acpi/vpd.asl> -#endif - #include <southbridge/intel/common/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 027fa08..fd91f64 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -31,11 +31,6 @@ #include <variant/acpi/mainboard.asl> } -#if CONFIG(CHROMEOS) - /* VPD support */ - #include <vendorcode/google/chromeos/acpi/vpd.asl> -#endif - #include <southbridge/intel/common/acpi/sleepstates.asl> #if CONFIG(EC_GOOGLE_WILCO) diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl deleted file mode 100644 index a1ea338..0000000 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This device provides an ACPI interface to read VPD keys from either - * the RO_VPD or RW_VPD region. For example: - * - * VPD.VPDF ("RO", "ro_key_name") - * VPD.VPDF ("RW", "rw_key_name") - */ - -Device (VPD) -{ - Name (_HID, "GOOG000F") - Name (_UID, 1) - Name (_STA, 0xf) - - Name (VOFS, 0x600) /* Start of VPD header in VPD region */ - Name (VIHL, 0x10) /* Length of VPD info header */ - Name (VPET, 0x00) /* VPD Entry Type: Terminator */ - Name (VPES, 0x01) /* VPD Entry Type: String */ - Name (VPEI, 0xfe) /* VPD Entry Type: Info (header) */ - Name (MORE, 0x80) /* Bit to indicate more length bytes */ - - Name (VPTR, Zero) /* Pointer to current byte in VPD for parser */ - Name (VEND, Zero) /* End of VPD region */ - - /* - * VLOC() - Return location and length of VPD region in memory. - * These values must be initialized in GNVS by coreboot. - * - * Returns: Package indicating start and length of region: - * [0] = Address of the start of VPD region. - * [1] = Length of the VPD region. - */ - Method (VLOC, 1, Serialized) - { - Switch (ToString (Arg0)) - { - Case ("RO") { - Return (Package () { \ROVP, \ROVL }) - } - Case ("RW") { - Return (Package () { \RWVP, \RWVL }) - } - Default { - Return (Package () { Zero, Zero }) - } - } - } - - /* - * VVPD() - Verify VPD info header. - * Arg0: VPD partition base address. - * Returns: VPD length or Zero if VPD header is not valid. - */ - Method (VVPD, 1, Serialized) - { - Local0 = Arg0 + ^VOFS - - OperationRegion (VPDH, SystemMemory, Local0, ^VIHL) - Field (VPDH, DWordAcc, NoLock, Preserve) - { - TYPE, 8, /* VPD Header Tag (=0xfe) */ - KLEN, 8, /* Key length (=9) */ - IVER, 8, /* Info version (=1) */ - SIGN, 64, /* Signature (="gVpdInfo") */ - VLEN, 8, /* Value length (=4) */ - SIZE, 32, /* VPD length */ - } - - If (TYPE != ^VPEI) { - Return (Zero) - } - If (KLEN != 9) { - Return (Zero) - } - If (IVER != 1) { - Return (Zero) - } - If (ToString (SIGN) != "gVpdInfo") { - Return (Zero) - } - If (VLEN != 4) { - Return (Zero) - } - - Return (SIZE) - } - - /* Return next byte from VPD at pointer VPTR, and increment VPTR. */ - Method (VPRB, 0, Serialized) - { - If (^VPTR > ^VEND) { - Printf ("Access beyond end of VPD region") - Return (Zero) - } - - Local0 = ^VPTR - OperationRegion (VPDR, SystemMemory, Local0, One) - Field (VPDR, DWordAcc, NoLock, Preserve) - { - BYTE, 8, - } - - /* Increment address pointer */ - ^VPTR++ - Return (BYTE) - } - - /* Extract and return next string from VPD. */ - Method (VPDE, 0, Serialized) - { - Local0 = One /* Indicates if there are more bytes */ - Local1 = Zero /* Length */ - - /* Decode the string length */ - While (Local0) { - /* Read the next byte at indicated address */ - Local2 = ^VPRB () - - /* Update the more bit from the byte in Local2 */ - Local0 = Local2 >> 7 - - /* Save the length bits from Local2 */ - Local1 <<= 7 - Local1 |= Local2 & 0x7f - } - If (Local1 == Zero) { - Return (Zero) - } - - /* Extract the string */ - Local3 = Zero - Local4 = "" - While (Local3 < Local1) { - Concatenate (Local4, ToString (^VPRB ()), Local4) - Local3++ - } - - Return (Local4) - } - - /* - * VPDS() - Find next VPD key and value. - * Returns: Package containing key and value: - * [0] = VPD key string - * [1] = VPD value string - */ - Method (VPDS, 0, Serialized) - { - Name (VPKV, Package () { "", "" }) - - /* Read the VPD type and ensure it is a string */ - If (^VPRB () != ^VPES) { - Printf ("VPDS: Type is not a string") - Return (VPKV) - } - - /* Extract the key string and value */ - VPKV[0] = VPDE () - VPKV[1] = VPDE () - - Return (VPKV) - } - - /* - * VPDF() - Find VPD key with matching name. - * Arg0: VPD Partition, either "RO" or "RW". - * Arg1: VPD key name to search for. - * Returns: VPD string corresponding to VPD key, or Zero if not found. - */ - Method (VPDF, 2, Serialized) - { - Local0 = VLOC (Arg0) - - /* Start of VPD region */ - ^VPTR = DerefOf (Local0[0]) - - /* End address of VPD region */ - ^VEND = ^VPTR + DerefOf (Local0[1]) - - If (^VPTR == Zero || ^VEND == Zero) { - Printf ("Unable to find VPD region") - Return (Zero) - } - - /* Verify VPD info header and save size */ - Local0 = VVPD (^VPTR) - If (Local0 == Zero) { - Printf ("VPD region %o did not verify", Arg0) - Return (Zero) - } - - /* Set VPD pointer to start of VPD entries */ - ^VPTR += ^VOFS + ^VIHL - - /* Search through VPD entries until key is found */ - Local1 = "" - While (Local1 != ToString (Arg1)) { - Local2 = VPDS () - Local1 = DerefOf (Local2[0]) - If (Local1 == "") { - Printf ("VPD KEY %o not found", Arg1) - Return (Zero) - } - } - Local3 = DerefOf (Local2[1]) - - Printf ("Found VPD KEY %o = %o", Local1, Local3) - Return (Local3) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/49902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Gerrit-Change-Number: 49902 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [WIP] coreboot_table: Expose VBNV offsets in lb_tables
by Kyösti Mälkki (Code Review) 04 Feb '21

04 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48786 ) Change subject: [WIP] coreboot_table: Expose VBNV offsets in lb_tables ...................................................................... [WIP] coreboot_table: Expose VBNV offsets in lb_tables Use CONFIG(VBOOT_VBNV_CMOS) ? Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/coreboot_table.c 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48786/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 20421ef..873845e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -189,10 +189,8 @@ } } -#if CONFIG(CHROMEOS) static void lb_vbnv(struct lb_header *header) { -#if CONFIG(PC80_SYSTEM) struct lb_range *vbnv; vbnv = (struct lb_range *)lb_new_record(header); @@ -200,9 +198,7 @@ vbnv->size = sizeof(*vbnv); vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; -#endif } -#endif /* CONFIG_CHROMEOS */ __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } @@ -490,10 +486,9 @@ if (CONFIG(CHROMEOS)) lb_gpios(head); -#if CONFIG(CHROMEOS) /* pass along VBNV offsets in CMOS */ - lb_vbnv(head); -#endif + if (CONFIG(CHROMEOS) && CONFIG(PC80_SYSTEM)) + lb_vbnv(head); /* Pass mmc early init status */ lb_mmc_info(head); -- To view, visit https://review.coreboot.org/c/coreboot/+/48786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36 Gerrit-Change-Number: 48786 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: coreboot_table: Drop <vboot/misc.h> include
by Kyösti Mälkki (Code Review) 04 Feb '21

04 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50249 ) Change subject: coreboot_table: Drop <vboot/misc.h> include ...................................................................... coreboot_table: Drop <vboot/misc.h> include Could have been removed with commit 63b9700b2c already. Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50249 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/lib/coreboot_table.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e00c2a4..86e0606 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -20,7 +20,6 @@ #include <bootmem.h> #include <bootsplash.h> #include <spi_flash.h> -#include <security/vboot/misc.h> #include <security/vboot/vbnv_layout.h> #include <smmstore.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf Gerrit-Change-Number: 50249 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021