coreboot-gerrit February 2021

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Change in coreboot[master]: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50242 ) Change subject: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build ...................................................................... vendorcode/amd/fsp/cezanne: add UPD structs from FSP build There will be incompatible changes during the further development of the coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct size to match the one in the FSP header. See CB:50241 for details. Signed-off-by: Justin Frodsham <justin.frodsham(a)protonmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242 Reviewed-by: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h M src/vendorcode/amd/fsp/cezanne/FspsUpd.h 2 files changed, 99 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved Justin Frodsham: Looks good to me, but someone else must approve diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 338133c..960d0b4 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -12,7 +12,61 @@ /** Fsp M Configuration **/ typedef struct __packed { - uint16_t UpdTerminator; + /** Offset 0x0040**/ uint32_t pci_express_base_addr; + /** Offset 0x0044**/ uint32_t serial_port_base; + /** Offset 0x0048**/ uint32_t serial_port_use_mmio; + /** Offset 0x004C**/ uint32_t serial_port_stride; + /** Offset 0x0050**/ uint32_t serial_port_baudrate; + /** Offset 0x0054**/ uint32_t serial_port_refclk; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; + /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; + /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; + /** Offset 0x0078**/ uint8_t aa_mode_en; + /** Offset 0x0079**/ uint8_t unused2; + /** Offset 0x007A**/ uint8_t unused3; + /** Offset 0x007B**/ uint8_t unused4; + /** Offset 0x007C**/ uint32_t fast_ppt_limit_mW; + /** Offset 0x0080**/ uint32_t slow_ppt_limit_mW; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s; + /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; + /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; + /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; + /** Offset 0x00A0**/ uint32_t stapm_time_constant_s; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms; + /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; + /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; + /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; + /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; + /** Offset 0x00C1**/ uint8_t system_config; + /** Offset 0x00C2**/ uint8_t core_dldo_bypass; + /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; + /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; + /** Offset 0x00C5**/ uint8_t unused5; + /** Offset 0x00C6**/ uint8_t unused6; + /** Offset 0x00C7**/ uint8_t sata_enable; + /** Offset 0x00C8**/ uint32_t tseg_size; + /** Offset 0x00CC**/ uint8_t pspp_policy; + /** Offset 0x00CD**/ uint8_t audio_soundwire; + /** Offset 0x00CE**/ uint8_t hd_audio_enable; + /** Offset 0x00CF**/ uint8_t unused9; + /** Offset 0x00D0**/ uint32_t bert_size; + /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0; + /** Offset 0x00D5**/ uint8_t ccx_down_core_mode; + /** Offset 0x00D6**/ uint8_t ccx_disable_smt; + /** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41]; + /** Offset 0x0100**/ uint16_t Reserved100; + /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index 2b7f19c..d4f8aea 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -10,7 +10,50 @@ #include <FspUpd.h> typedef struct __packed { - uint16_t UpdTerminator; + /** Offset 0x0020**/ uint32_t emmc0_mode; + /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x0029**/ uint8_t unused0[7]; + /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; + /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; + /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; + /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; + /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; + /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; + /** Offset 0x0090**/ uint8_t dxio_descriptor6[16]; + /** Offset 0x00A0**/ uint8_t dxio_descriptor7[16]; + /** Offset 0x00B0**/ uint8_t unused1[16]; + /** Offset 0x00C0**/ uint32_t ddi_descriptor0; + /** Offset 0x00C4**/ uint32_t ddi_descriptor1; + /** Offset 0x00C8**/ uint32_t ddi_descriptor2; + /** Offset 0x00CC**/ uint32_t ddi_descriptor3; + /** Offset 0x00D0**/ uint8_t unused2[16]; + /** Offset 0x00E0**/ uint8_t fch_usb_version_major; + /** Offset 0x00E1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00E2**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x00EB**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x00F4**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x00FD**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x0106**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x010F**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x0118**/ uint8_t fch_usb_device_removable; + /** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x011D**/ uint8_t unused3; + /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; + /** Offset 0x0122**/ uint8_t xhci0_force_gen1; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; + /** Offset 0x0130**/ uint8_t unused4[16]; + /** Offset 0x0140**/ uint8_t UnusedUpdSpace1[16]; + /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/50242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Gerrit-Change-Number: 50242 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Justin Frodsham, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50242 ) Change subject: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: the UPDs are expected to change quite a bit during the development and there will be improvements for sure. but to get to a point where we get far enough to be able to test and develop code that runs after calling into the fsp-m, we need matching UPDs on both sides right now or the fsp-m will just hang and this is the current work in progress state from the cezanne fsp -- To view, visit https://review.coreboot.org/c/coreboot/+/50242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Gerrit-Change-Number: 50242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 01:36:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Fill ECC type in romstage
by Jingle Hsu (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Christian Walter, Angel Pons, Arthur Heymans, Morgan Jang. Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50179 ) Change subject: mb/ocp/deltalake: Fill ECC type in romstage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It wasn't I verified it's correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/50179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Gerrit-Change-Number: 50179 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 01:26:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/libpayload/arch/arm64/mmu.c: Fix typo in comment
by Julius Werner (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: HAOUAS Elyes. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50268 ) Change subject: payloads/libpayload/arch/arm64/mmu.c: Fix typo in comment ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb10a881ef1d983f11318f0f6934491fd19fd0bf Gerrit-Change-Number: 50268 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 04 Feb 2021 01:15:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add UPD for USB3 phy setting adjust
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, chris wang. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50240 ) Change subject: soc/amd/picasso: add UPD for USB3 phy setting adjust ...................................................................... Patch Set 7: (5 comments) File src/soc/amd/picasso/chip.h: https://review.coreboot.org/c/coreboot/+/50240/comment/781144cd_46590575 PS7, Line 75: #define USB3_PORT_COUNT 4 only true for dali/pollock. picasso has an additional usb3 port on xhci1, so this should be changed to 5; the devices with only 4 usb3 ports then just ignore the last one https://review.coreboot.org/c/coreboot/+/50240/comment/c7e02b35_56d4f1e6 PS7, Line 258: uint8_t usb3_phy_en; i wonder if just having one setting to enable all usb3 port overrides would be sufficient. if the override is not selected, then just the defaults are used, no no board will break if it doesn't have all those settings in the devicetree, and if not then just all values have to be provided? not sure if having enable bits for the various settings is something that's needed. haven't looked closely at the fsp patch though, so i'm not sure https://review.coreboot.org/c/coreboot/+/50240/comment/b340a6d3_dfaf3253 PS7, Line 258: usb3_phy_en usb3_phy_override would be a much more descriptive name. from the name i'd assume that it's for enabling the usb3 part of the usb ports, which isn't what it does File src/vendorcode/amd/fsp/picasso/FspsUpd.h: https://review.coreboot.org/c/coreboot/+/50240/comment/b39c3f8a_a06aa5cf PS7, Line 58: /** Offset 0x013D**/ uint8_t usb_3_port0_phy_tune[2]; : /** Offset 0x013F**/ uint8_t usb_3_port1_phy_tune[2]; : /** Offset 0x0141**/ uint8_t usb_3_port2_phy_tune[2]; : /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2]; you could do something like i did for the fch_usb_2_port_phy_tune setting above. that allows to just loop over the ports and apply the settings to the upd fields. i'm ok with both. feel free to keep it as it is right now and just ack this comment; that's someting that could be also done in the future. https://review.coreboot.org/c/coreboot/+/50240/comment/6d8188ad_f783d3b7 PS7, Line 61: /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2]; there are 5 usb3 ports on the picasso chips; dali/pollock have 4 only. so there's the data structure for the last port missing -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 7 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 01:05:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: chris wang. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50212/comment/ba2f4115_602bca50 PS7, Line 32: > For such changes, it is important to add Cq-Depend to ensure that when it lands in chromium tree, th […] since the fsp side change to use the upds isn't merged yet, only the change id of this patch in the cros review system really needs to be added to the fsp-side patch in there as cq-depend. if there are incompatible upd changes, it's important to add the circular cq-depends tags in both patches and the one on the fsp patch canonly be added when the coreboot one is already submitted in upstream and pulled into the cros repos. since that has a bit more potential for disaster, i wanted to have everything in good shape before the fsp patch gets merged. but if in doubt ask Furquan or Martin about the cros commit queue dependency thing; i think i just pinged them when i needed to make an incompatible upd change when there were already images for zork devices built automatically -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 7 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 00:37:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/common/block/acpi/pm_state: fix comparison in get_index_bit
by 9elements QA (Code Review) 04 Feb '21

04 Feb '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50243 ) Change subject: amd/common/block/acpi/pm_state: fix comparison in get_index_bit ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 4/1/5 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : FAIL : https://lava.9esec.io/r/40999 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/40995 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/40994 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/40993 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/40992 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/50243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7 Gerrit-Change-Number: 50243 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 00:33:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
by Marshall Dawson (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh, Meera Ravindranath, Andrey Petrov, Patrick Rudolph, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50241 ) Change subject: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/50241/comment/d1370e1e_a3a84b85 PS1, Line 242: != What about <= instead of !=? Assuming UPD only grows at the end, that would allow flexibility to update the binaries, then update the header file to match. -- To view, visit https://review.coreboot.org/c/coreboot/+/50241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Gerrit-Change-Number: 50241 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 00:29:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50244 ) Change subject: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers ...................................................................... soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers Picasso has 32 configurable GPEs, not only 28. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index d45c3b0..60fd6f9 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -75,6 +75,10 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK0_REQ_SHIFT 0 @@ -135,10 +139,6 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ -#define PM1_LIMIT 16 -#define GPE0_LIMIT 28 -#define TOTAL_BITS(a) (8 * sizeof(a)) - /* SATA Controller D11F0 */ #define SATA_MISC_CONTROL_REG 0x40 #define SATA_MISC_SUBCLASS_WREN BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/50244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Gerrit-Change-Number: 50244 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/common/block/acpi/pm_state: fix comparison in get_index_bit
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50243 ) Change subject: amd/common/block/acpi/pm_state: fix comparison in get_index_bit ...................................................................... amd/common/block/acpi/pm_state: fix comparison in get_index_bit In the case of passing 32 as limit the code returned -1, but should have continued, since 32 is a valid value here. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50243 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/acpi/pm_state.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c index a009718..05bb927 100644 --- a/src/soc/amd/common/block/acpi/pm_state.c +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -13,7 +13,7 @@ uint16_t i; uint32_t t; - if (limit >= TOTAL_BITS(uint32_t)) + if (limit > TOTAL_BITS(uint32_t)) return -1; /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7 Gerrit-Change-Number: 50243 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021