coreboot-gerrit February 2021

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Change in coreboot[master]: mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50271 ) Change subject: mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM ...................................................................... mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM BUG=b:178681161 TEST=abuild Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/memory/Makefile.inc M src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/50271/1 diff --git a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc index 03a38b2..b8229c4 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt index 93934ae..45b69ae 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt @@ -1,2 +1,3 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:F 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) diff --git a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt index fb014a3..5f83732 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt @@ -1 +1,2 @@ MT53E512M32D2NP-046 WT:F +H9HCNNNBKMMLXR-NEE -- To view, visit https://review.coreboot.org/c/coreboot/+/50271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Gerrit-Change-Number: 50271 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Replace the PSP Bootloader with AB version
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50251 ) Change subject: soc/amd/cezanne: Replace the PSP Bootloader with AB version ...................................................................... Patch Set 1: -Code-Review (1 comment) Patchset: PS1: with this patch the board gets stuck at post code 00000000, so we probably need an updated psp bl -- To view, visit https://review.coreboot.org/c/coreboot/+/50251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcee65e7dcc30d7ee7a58338f439eaee5cd942e Gerrit-Change-Number: 50251 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 03 Feb 2021 22:01:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... soc/amd/cezanne/fch: add ACPI I/O port setup The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from the reference code, but not the PPR. I've submitted a change request for the PPR, so this mismatch might go away in the future. The case for HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends up being identical to the function in soc/amd/picasso, I'll move it to the common AMD SoC code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/50270/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index f853ece..5fb4f0a 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -1,9 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> +#include <assert.h> +#include <soc/iomap.h> #include <soc/southbridge.h> +static void fch_init_acpi_ports(void) +{ + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* TODO: add code for SMI handler case */ + dead_code(); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + void fch_init(void *chip_info) { + fch_init_acpi_ports(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 20f7037..00de438 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -16,6 +16,16 @@ /* I/O Ranges */ #define NCP_ERR 0x00f0 +#define CEZANNE_ACPI_IO_BASE 0x0400 +#define ACPI_PM_EVT_BLK (CEZANNE_ACPI_IO_BASE + 0x00) +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) +#define ACPI_PM1_CNT_BLK (CEZANNE_ACPI_IO_BASE + 0x04) +#define ACPI_PM_TMR_BLK (CEZANNE_ACPI_IO_BASE + 0x08) +#define ACPI_CPU_CONTROL (CEZANNE_ACPI_IO_BASE + 0x10) +#define ACPI_GPE0_BLK (CEZANNE_ACPI_IO_BASE + 0x20) +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) #define SMB_BASE_ADDR 0x0b00 #endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index a38d706..8623063 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -8,7 +8,37 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboards: Remove default CHROMEOS=y
by Furquan Shaikh (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Kyösti Mälkki. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50118 ) Change subject: mainboards: Remove default CHROMEOS=y ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Gerrit-Change-Number: 50118 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:30:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/google/chromeos: Drop <acpi/vpd.asl>
by Furquan Shaikh (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Lance Zhao, Kyösti Mälkki. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49902 ) Change subject: vc/google/chromeos: Drop <acpi/vpd.asl> ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Gerrit-Change-Number: 49902 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:28:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_table: Move VBOOT_VBNV support
by Furquan Shaikh (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Kyösti Mälkki, Aaron Durbin. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50250 ) Change subject: coreboot_table: Move VBOOT_VBNV support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187 Gerrit-Change-Number: 50250 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:28:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_table: Drop <vboot/misc.h> include
by Furquan Shaikh (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Kyösti Mälkki. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50249 ) Change subject: coreboot_table: Drop <vboot/misc.h> include ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf Gerrit-Change-Number: 50249 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:20:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/../chromeos.asl: Drop CHROMEOS guard
by Furquan Shaikh (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Kyösti Mälkki. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50248 ) Change subject: vc/../chromeos.asl: Drop CHROMEOS guard ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143 Gerrit-Change-Number: 50248 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:18:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/haswell: Create RMRR for iGPU
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46990 ) Change subject: nb/intel/haswell: Create RMRR for iGPU ...................................................................... nb/intel/haswell: Create RMRR for iGPU Taken from Broadwell. Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46990/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 0e7967f..f48ef61 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -63,6 +63,21 @@ acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + const struct device *sa_dev = pcidev_on_root(0, 0); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Gerrit-Change-Number: 46990 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Configure USB2 port for Type-C
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50217 ) Change subject: mb/google/volteer/variants/drobit: Configure USB2 port for Type-C ...................................................................... mb/google/volteer/variants/drobit: Configure USB2 port for Type-C USB2 ports assigned to type-C connector need to be configured properly by the USB2_PORT_TYPE_C. and also modify the description of USB port. BUG=b:177480902 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the typeC port function is normal by manual. Signed-off-by: Wayne3_Wang <Wayne3_Wang(a)pegatron.corp-partner.google.com> Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217 Reviewed-by: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Wayne3 Wang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 17143b8..608535e 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -21,6 +21,9 @@ .tdp_pl4 = 105, }" + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # Type-C port 0 + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -178,7 +181,7 @@ device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref tcss_usb3_port2 on @@ -192,13 +195,13 @@ chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port4 on @@ -223,7 +226,7 @@ device ref usb2_port10 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb3_port1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Gerrit-Change-Number: 50217 Gerrit-PatchSet: 2 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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2014

2013

coreboot-gerrit February 2021