coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/tgl: Add configurable value for ConfigTdpLevel
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50104 ) Change subject: soc/intel/tgl: Add configurable value for ConfigTdpLevel ...................................................................... soc/intel/tgl: Add configurable value for ConfigTdpLevel According to Tigerlake TDP specifications (doc #575683, table 4-2), TGL supports different TDP levels depends on CPU segement/package, IA Cores and graphics configuration. For example, UP3 4-Core GT2 suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable TDP-Down_2=12W. This configurable value can be used to select suitable TDP level Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/tigerlake/chip.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 2 files changed, 10 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d3062cc..edc7160 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -105,6 +105,9 @@ /* Common struct containing power limits configuration information */ struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX]; + /* Configuration for boot TDP selection; */ + uint8_t ConfigTdpLevel; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 35cc43b..909ba36 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -1304,9 +1304,14 @@ **/ UINT8 IsTPMPresence; -/** Offset 0x0389 - Reserved +/** Offset 0x0389 - ConfigTdpLevel + Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ - UINT8 Reserved17[6]; + UINT8 ConfigTdpLevel; + +/** Offset 0x038A - Reserved +**/ + UINT8 Reserved17[5]; /** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. -- To view, visit https://review.coreboot.org/c/coreboot/+/50104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Gerrit-Change-Number: 50104 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Change cTDP level to level 2 (15W)
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Nick Vaccaro, Derek Huang, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50105 ) Change subject: mb/google/volteer: Change cTDP level to level 2 (15W) ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50105/comment/7bfff8db_2c7fed51 PS2, Line 12: 4-2 > Not sure if I am referring to the latest version of EDS, I am referring to rev1.4, page 87. […] Ah ok I have 1.6, it's called out as 4-2 Patchset: PS2: > There is no bug for this, shall I create a bug? Yes, please. I'm concerned what effect this may have on existing thermal solutions for these variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/50105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4420a6a2e463b0a6bd7eb4b81f6a4fb975895ea3 Gerrit-Change-Number: 50105 Gerrit-PatchSet: 2 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:10:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50269 to look at the new patch set (#2). Change subject: soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment ...................................................................... soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/skylake/acpi/irqlinks.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/50269/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879 Gerrit-Change-Number: 50269 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/voema: Enable EEPROM for OV2740
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50216 ) Change subject: mb/google/volteer/var/voema: Enable EEPROM for OV2740 ...................................................................... mb/google/volteer/var/voema: Enable EEPROM for OV2740 Add ACPI entries for AT24 NVM device. BUG=b:169551066 TEST=Build and run for basic camera functions. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jim Lai <jim.lai(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl 1 file changed, 66 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jim Lai: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl index 53f5d03..4ef83fd3 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -271,4 +271,70 @@ } }) } + Device (NVM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_DDN, "AT24 EEPROM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0050, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM1 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x06) + { + Package (0x02) + { + "size", + 0x2000 + }, + Package (0x02) + { + "pagesize", + One + }, + Package (0x02) + { + "read-only", + One + }, + Package (0x02) + { + "address-width", + 0x10 + }, + Package (0x02) + { + "compatible", + "atmel,24c64" + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } + } + }) + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/50216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab Gerrit-Change-Number: 50216 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mainboards: Remove default CHROMEOS=y
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50118 ) Change subject: mainboards: Remove default CHROMEOS=y ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: intel RVP boards probably aren't a big deal, either -- To view, visit https://review.coreboot.org/c/coreboot/+/50118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Gerrit-Change-Number: 50118 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboards: Remove default CHROMEOS=y
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50118 ) Change subject: mainboards: Remove default CHROMEOS=y ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: +2 for the google boards, our additional configs already contain CONFIG_CHROMEOS=y for all of these google boards -- To view, visit https://review.coreboot.org/c/coreboot/+/50118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Gerrit-Change-Number: 50118 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 20:04:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50209 ) Change subject: soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports ...................................................................... soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports There's no dedicated south bridge any more and now we have integrated FCHs in the SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index fa99db8..e6cd51a 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -115,7 +115,7 @@ } } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -220,7 +220,7 @@ void fch_init(void *chip_info) { i2c_soc_init(); - sb_init_acpi_ports(); + fch_init_acpi_ports(); acpi_pm_gpe_add_events_print_events(); gpio_add_events(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2a91596..2a78ff9 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -356,7 +356,7 @@ printk(BIOS_DEBUG, "%s\n", __func__); } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -406,7 +406,7 @@ { struct chipset_power_state *state; - sb_init_acpi_ports(); + fch_init_acpi_ports(); state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); if (state) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d Gerrit-Change-Number: 50209 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: remove UART2/3 AOAC device offsets
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50230 ) Change subject: soc/amd/cezanne: remove UART2/3 AOAC device offsets ...................................................................... soc/amd/cezanne: remove UART2/3 AOAC device offsets UART2 and UART3 don't exist on Cezanne which now has been verified, so remove the corresponding AOAC offsets. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 6949fa5..a38d706 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -22,9 +22,7 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 /* IO 0xf0 NCP Error */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 Gerrit-Change-Number: 50230 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: console/vtxprintf.c: Correct code style
by Nico Huber (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Frans Hendriks, Julius Werner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49960 ) Change subject: console/vtxprintf.c: Correct code style ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I'm not a fan of changing existing code style unless there is a strong rule about it. Yes, braces are not necessary, but we have discussed multiple times in the community that they can help the reader and maintenance etc. Maybe checkpatch should be updated in that regard? The switch/case statement looks like a nice, easy to read table and I guess that's what the author intended. So why apply any rule if it decreases readability? -- To view, visit https://review.coreboot.org/c/coreboot/+/49960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb200bf7dd1ef7632aa4e1213bce72d9165560c9 Gerrit-Change-Number: 49960 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 19:44:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpi/pm_state: add missing include
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50266 ) Change subject: soc/amd/common/block/acpi/pm_state: add missing include ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I think <amdblocks/acpi.h> is included and not used here : src/soc/amd/picasso/acpi.c src/soc/amd/picasso/include/soc/acpi.h src/soc/amd/stoneyridge/acpi.c src/soc/amd/stoneyridge/include/soc/acpi.h -- To view, visit https://review.coreboot.org/c/coreboot/+/50266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2 Gerrit-Change-Number: 50266 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Feb 2021 19:41:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021