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Change subject: soc/amd/picasso: add UPD for USB3 phy setting adjust
......................................................................
Patch Set 7:
(4 comments)
File src/soc/amd/picasso/chip.h:
https://review.coreboot.org/c/coreboot/+/50240/comment/83138762_2efe22ef
PS7, Line 75: #define USB3_PORT_COUNT 4
> only true for dali/pollock. […]
Yes, check with the design guide, the USB3 phy setting should only apply to controller 0. so that only got 4 ports and in the Pollock-PI and Picasso-PI, it also only apply to 4 ports. I will rename the definition to make it clear.
https://review.coreboot.org/c/coreboot/+/50240/comment/c6eb884a_f9ca5c18
PS7, Line 258: uint8_t usb3_phy_en;
> i wonder if just having one setting to enable all usb3 port overrides would be sufficient. […]
Yes, I add the default value in the tremyle and delboz's devtree, but agree with you that to have a setting for usb3 phy override might be better.
File src/vendorcode/amd/fsp/picasso/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/50240/comment/23e2bda6_3e0878ce
PS7, Line 61: /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2];
> there are 5 usb3 ports on the picasso chips; dali/pollock have 4 only. […]
those port should belong to controller 0 and in our Picasso-PI or Pollock-PI. it only to apply those port for tuning
https://review.coreboot.org/c/coreboot/+/50240/comment/7566596e_84e4f0a5
PS7, Line 58: /** Offset 0x013D**/ uint8_t usb_3_port0_phy_tune[2];
: /** Offset 0x013F**/ uint8_t usb_3_port1_phy_tune[2];
: /** Offset 0x0141**/ uint8_t usb_3_port2_phy_tune[2];
: /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2];
> you could do something like i did for the fch_usb_2_port_phy_tune setting above. […]
Sure, so that need have a define like FSPS_UPD_USB2_PORT_COUNT. I will check that.
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Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
......................................................................
vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a
new dependency within the file MemInfoHob.h. Adding required macros to
resolve the dependency.
BUG=b:178846328
Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
1 file changed, 10 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50254/3
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Change subject: mb/google/dedede: Modify USB 3.0 PHY parameters for galith
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50253/comment/34a79a1e_bfa84256
PS2, Line 7: galith
> galtic ?
because galith keep going now
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Change subject: soc/amd/cezanne: populate some FSP-M UPDs
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/cezanne/romstage.c:
https://review.coreboot.org/c/coreboot/+/50239/comment/cf484666_d43faae0
PS2, Line 19: 1
> ah, DRIVERS_UART_8250MEM and DRIVERS_UART_8250MEM_32 only get selected together, so this is indeed f […]
Done
https://review.coreboot.org/c/coreboot/+/50239/comment/dd383286_68289e74
PS2, Line 19: serial_port_stride
> Do we need to pass in the baud clock? Or does FSP-M assume the baud rate has already been set?
added that to match what picasso does for now; since during bringup we'll only use the internal uart the defaults were sane though. refclk, baudrate and stride will probably be removed after the initial bringup is done
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Change subject: soc/amd/cezanne: populate some FSP-M UPDs
......................................................................
soc/amd/cezanne: populate some FSP-M UPDs
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee
---
M src/soc/amd/cezanne/romstage.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50239/3
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Change subject: mb/google/zork: update telemetry settings for Woomax
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Patch Set 2: Code-Review+2
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