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Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
......................................................................
Patch Set 12:
(2 comments)
File src/drivers/intel/fsp2_0/Kconfig.debug_blob:
https://review.coreboot.org/c/coreboot/+/45905/comment/10826427_facae800
PS5, Line 46: using new header 'FirmwareVersionInfo.h'.
> > hi, i am confused here about the automatic detection how you are proposing here. […]
Ohh.. thanks Nico for detail explanation.. I think lets move ahead with current implementation .. then we can optimize it further..
File src/drivers/intel/fsp2_0/hand_off_block.c:
https://review.coreboot.org/c/coreboot/+/45905/comment/a9719625_358ff8d2
PS12, Line 226: #elif
> both can work […]
as discussed with you marking as resolved.
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Tim Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50181 )
Change subject: mb/ocp/deltalake: Override mainboard board type
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/ocp/deltalake/ramstage.c:
https://review.coreboot.org/c/coreboot/+/50181/comment/30456cff_0f7c249a
PS1, Line 62: return SMBIOS_BOARD_TYPE_SERVER_BLADE;
> I don't think this is a blade server so I use "motherboard" in CB:48850.
If it should be blade server I can abandon my patch.
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Change subject: soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
fine by me since it's getting dropped in the next patch in the series
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Change subject: mb/ocp/deltalake: Override mainboard board type
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/ocp/deltalake/ramstage.c:
https://review.coreboot.org/c/coreboot/+/50181/comment/00046828_da84431e
PS1, Line 62: return SMBIOS_BOARD_TYPE_SERVER_BLADE;
I don't think this is a blade server so I use "motherboard" in CB:48850.
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Change subject: mb/purism/librem_cnl: Implement `die_notify`
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
tested ok on a Librem Mini v2, but as-is requires all future variants (like the upcoming Librem 14) include their own die.c which I'm not sure is ideal
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Change subject: mainboards: Remove default CHROMEOS=y
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
We should prepare the chorme ToT CL for this when this CL UPSTREAM to our tree.
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Change subject: mb/ocp/deltalake: Fill ECC type in romstage
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/picasso: add UPD for USB3 phy setting adjust
......................................................................
Patch Set 8:
(3 comments)
File src/soc/amd/picasso/chip.h:
https://review.coreboot.org/c/coreboot/+/50240/comment/a28b4119_82148bd0
PS7, Line 258: usb3_phy_en
> usb3_phy_override would be a much more descriptive name. […]
Done
https://review.coreboot.org/c/coreboot/+/50240/comment/35aa97c3_2b09f7de
PS7, Line 258: uint8_t usb3_phy_en;
> Yes, I add the default value in the tremyle and delboz's devtree, but agree with you that to have a […]
Done
File src/vendorcode/amd/fsp/picasso/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/50240/comment/8d28addf_875833c2
PS7, Line 58: /** Offset 0x013D**/ uint8_t usb_3_port0_phy_tune[2];
: /** Offset 0x013F**/ uint8_t usb_3_port1_phy_tune[2];
: /** Offset 0x0141**/ uint8_t usb_3_port2_phy_tune[2];
: /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2];
> Sure, so that need have a define like FSPS_UPD_USB2_PORT_COUNT. I will check that.
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Chris Wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50240
to look at the new patch set (#8).
Change subject: soc/amd/picasso: add UPD for USB3 phy setting adjust
......................................................................
soc/amd/picasso: add UPD for USB3 phy setting adjust
add UPD for USB3 phy setting adjust
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
---
M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
M src/vendorcode/amd/fsp/picasso/FspsUpd.h
5 files changed, 138 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50240/8
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