coreboot-gerrit February 2021

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Change in coreboot[master]: mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50218 ) Change subject: mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes ...................................................................... mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50218 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/amd/parmer/bootblock.c M src/mainboard/amd/thatcher/bootblock.c 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/amd/parmer/bootblock.c b/src/mainboard/amd/parmer/bootblock.c index 29f7abb..ccd8ec1 100644 --- a/src/mainboard/amd/parmer/bootblock.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <device/pci_ops.h> void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 468c938..e01131d 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -2,7 +2,6 @@ #include <amdblocks/acpimmio.h> #include <bootblock_common.h> -#include <device/pci_ops.h> #include <console/console.h> #include <superio/smsc/lpc47n217/lpc47n217.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Gerrit-Change-Number: 50218 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/majolica: add fmd for use when building chromeos
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50208 ) Change subject: mb/amd/majolica: add fmd for use when building chromeos ...................................................................... mb/amd/majolica: add fmd for use when building chromeos BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/majolica/Kconfig A src/mainboard/amd/majolica/chromeos.fmd 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index ce8a498..ef0aa20 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -10,6 +10,7 @@ config FMDFILE string + default "src/mainboard/amd/majolica/chromeos.fmd" if CHROMEOS default "src/mainboard/amd/majolica/board.fmd" config MAINBOARD_DIR diff --git a/src/mainboard/amd/majolica/chromeos.fmd b/src/mainboard/amd/majolica/chromeos.fmd new file mode 100644 index 0000000..90cf2eb --- /dev/null +++ b/src/mainboard/amd/majolica/chromeos.fmd @@ -0,0 +1,14 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + RW_LEGACY(CBFS) 4K + FW_MAIN_A(CBFS) 1M + VBLOCK_A 8K + FW_MAIN_B(CBFS) 1M + VBLOCK_B 8K + SHARED_DATA 8K + FMAP 4K + COREBOOT(CBFS) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Gerrit-Change-Number: 50208 Gerrit-PatchSet: 3 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/purism/librem_cnl: Implement `die_notify`
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50013 ) Change subject: mb/purism/librem_cnl: Implement `die_notify` ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > tested ok on a Librem Mini v2, but as-is requires all future variants (like the upcoming Librem 14) […] Hmmm... Good point. I could try using a `wildcard` (optionally adds a file to be built), or move die.c out of variants and define the LED GPIO in a per-variant header. -- To view, visit https://review.coreboot.org/c/coreboot/+/50013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Gerrit-Change-Number: 50013 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 09:54:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50086 ) Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 ...................................................................... soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 A minimum of 100ms delay is required before sending a configuration request to the downstream components. Since the kernel already adds 100ms, this change drops the extra 100ms delay in TBT PCIe root ports _PS0 method in order to improve resume time. BUG=b:177519081 TEST=Boot to kernel and validated various tests on Voxel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Sukumar Ghorai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 08d8900..39180f7 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -196,8 +196,6 @@ If (PMEX == 1) { PMEX = 0 /* Disable Power Management SCI */ } - - Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ } Method (_PS3, 0, Serialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/50086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Gerrit-Change-Number: 50086 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu: Fix SMP boot
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50235 ) Change subject: mb/emulation/qemu: Fix SMP boot ...................................................................... mb/emulation/qemu: Fix SMP boot Fix booting with SMP enabled, when specifying more CPUs than supported by the code. Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/northbridge.c 2 files changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 641cea8..a22d7f9 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -44,8 +44,8 @@ config MAX_CPUS int - default 4 if SMM_ASEG - default 32 + default 32 if SMM_TSEG + default 4 config CPU_QEMU_X86_64 bool "Experimental 64bit support" diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f49d47da..80fba1d 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -271,6 +271,12 @@ if (max_cpus < 0) return; + /* + * Do not install more CPUs than supported by coreboot. + * This will cause a buffer overflow where fixed arrays of CONFIG_MAX_CPUS + * are used and might result in a boot failure. + */ + max_cpus = MIN(max_cpus, CONFIG_MAX_CPUS); /* * TODO: This only handles the simple "qemu -smp $nr" case -- To view, visit https://review.coreboot.org/c/coreboot/+/50235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Gerrit-Change-Number: 50235 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <bootstate.h>
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50203 ) Change subject: src: Remove unused <bootstate.h> ...................................................................... src: Remove unused <bootstate.h> Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/zork/mainboard.c M src/mainboard/ocp/deltalake/ramstage.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cse/cse_lite.c 5 files changed, 1 insertion(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 23b1596..fabdc5e 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> -#include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 0da47a3..1558245 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -25,7 +25,6 @@ #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> #include <commonlib/helpers.h> -#include <bootstate.h> #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 40810b6..dc70eb2 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -2,7 +2,6 @@ #include <assert.h> #include <console/console.h> -#include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f96a2d7..e7f3f0d 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -5,7 +5,6 @@ #include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <bootstate.h> #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/turbo.h> diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 036a50a..62c274b 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> + #include <console/console.h> #include <boot_device.h> #include <cbfs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Gerrit-Change-Number: 50203 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <cbfs.h>
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50166 ) Change subject: src: Remove unused <cbfs.h> ...................................................................... src: Remove unused <cbfs.h> Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/zork/mainboard.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/soc/amd/common/block/psp/psp_smm.c 8 files changed, 1 insertion(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 88487d5..59e949a 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 88487d5..59e949a 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 9c32314..093a88c 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 8d43464..67f71d6e 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 06270b8..8ba76ac 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 1de593e..0da47a3 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -2,7 +2,6 @@ #include <string.h> #include <console/console.h> -#include <cbfs.h> #include <device/device.h> #include <device/mmio.h> #include <acpi/acpi.h> diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 50ba1b3..5b02e78 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include <assert.h> #include <console/console.h> #include <fsp/api.h> @@ -7,7 +8,6 @@ #include <string.h> #include <soc/meminit.h> #include <baseboard/variants.h> -#include <cbfs.h> #include "board_id.h" #define SPD_ID_MASK 0x7 diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 92b0cc6..7c15616 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cbfs.h> #include <region_file.h> #include <rules.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b Gerrit-Change-Number: 50166 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h>
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50196 ) Change subject: soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h> ...................................................................... soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h> Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50196 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/sc7180/aop_load_reset.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index eb90f86..86ee993 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> +#include <program_loading.h> #include <soc/mmu.h> #include <soc/aop.h> #include <soc/clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b Gerrit-Change-Number: 50196 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8192/spm.c: Add missing <string.h>
by Patrick Georgi (Code Review) 04 Feb '21

04 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50168 ) Change subject: soc/mediatek/mt8192/spm.c: Add missing <string.h> ...................................................................... soc/mediatek/mt8192/spm.c: Add missing <string.h> Change-Id: I56a4e0fb42c881026f4ee1abe30f9b356af6a68f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50168 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index f080a11..13eebc8 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <cbfs.h> #include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/mcu_common.h> #include <soc/spm.h> #include <soc/symbols.h> +#include <string.h> #include <timer.h> #define SPM_SYSTEM_BASE_OFFSET 0x40000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/50168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a4e0fb42c881026f4ee1abe30f9b356af6a68f Gerrit-Change-Number: 50168 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: device/i2c_bus.c: Correct code style
by Angel Pons (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Frans Hendriks, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50190 ) Change subject: device/i2c_bus.c: Correct code style ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Gerrit-Change-Number: 50190 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 09:49:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021