Change in coreboot[master]: nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50231 )

Change subject: nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`
......................................................................

nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`

This partially reverts:

- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e

It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.

Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: HAOUAS Elyes 
---
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/ironlake/bootblock.c
M src/northbridge/intel/sandybridge/bootblock.c
M src/northbridge/intel/x4x/bootblock.c
6 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index e2cabdb..a9a1e8e 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "gm45.h"
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 0bb8ae2..1336582 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "haswell.h"
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index edb9a8d..448d5e4 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "i945.h"
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 02b63a6..6610a3e 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "ironlake.h"
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 92f9aee..1eba744 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "sandybridge.h"
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index aedcdd9..f15d181 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -2,8 +2,8 @@

#include <arch/bootblock.h>
 #include <arch/mmio.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "x4x.h"