coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

1 participants
2457 discussions

Change in coreboot[master]: mb/google/kukui: indent config names for burnet and esche
by Hung-Te Lin (Code Review) 03 Aug '20

03 Aug '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43986 ) Change subject: mb/google/kukui: indent config names for burnet and esche ...................................................................... mb/google/kukui: indent config names for burnet and esche The 'burnet' and 'esche' in Kcofig.name should have two spaces after the arrow. BUG=None TEST=make menuconfig BRANCH=kukui Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig.name 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/43986/1 diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 77cdc67..ecfb86e 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -51,9 +51,9 @@ select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_ESCHE - bool "-> Esche" + bool "-> Esche" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_BURNET - bool "-> Burnet" + bool "-> Burnet" select BOARD_GOOGLE_JACUZZI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/43986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Gerrit-Change-Number: 43986 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: Doc/mb/facebook/monolith: Remove plural *s*
by Paul Menzel (Code Review) 03 Aug '20

03 Aug '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44018 ) Change subject: Doc/mb/facebook/monolith: Remove plural *s* ...................................................................... Doc/mb/facebook/monolith: Remove plural *s* Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf --- M Documentation/mainboard/facebook/monolith.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44018/1 diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index cdd3208..6e30496 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -2,7 +2,7 @@ This page describes how to run coreboot on the Facebook Monolith. -Please note: the coreboot implementation for this boards is in its +Please note: the coreboot implementation for this board is in its Beta state and isn't fully tested yet. ## Required blobs -- To view, visit https://review.coreboot.org/c/coreboot/+/44018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf Gerrit-Change-Number: 44018 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: Doc: mb/lenovo: Mark up file name as code/monospace
by Paul Menzel (Code Review) 03 Aug '20

03 Aug '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43748 ) Change subject: Doc: mb/lenovo: Mark up file name as code/monospace ...................................................................... Doc: mb/lenovo: Mark up file name as code/monospace Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/mainboard/lenovo/montevina_series.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/43748/1 diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e8796..c886a21 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -89,7 +89,7 @@ ``` If your flash is not 8 MB, you need to change values of `flcomp_density1` and -`flreg1_limit` in the ifd-x200.set file according to following table: +`flreg1_limit` in the `ifd-x200.set` file according to following table: ```eval_rst +-----------------+-------+-------+--------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/43748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4 Gerrit-Change-Number: 43748 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drivers/amd/i2s_machine_dev: return if scope is NULL
by Martin Roth (Code Review) 03 Aug '20

03 Aug '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44001 ) Change subject: drivers/amd/i2s_machine_dev: return if scope is NULL ...................................................................... drivers/amd/i2s_machine_dev: return if scope is NULL Avoid dereferencing a null pointer. Found-by: Coverity CID 1430549 BUG=None TEST=Build Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I53f6a38aac6e7f94c3c370996b3b82ca0d88dac4 --- M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44001/1 diff --git a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c index a938265..b5be31d 100644 --- a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c +++ b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c @@ -21,6 +21,11 @@ dmic_select_gpio = &cfg->dmic_select_gpio; + if (scope == NULL) { + printk(BIOS_ERR, "%s: ERROR: ACPI I2S scope not found\n", dev_path(dev)); + return; + } + if (cfg->hid == NULL) { printk(BIOS_ERR, "%s: ERROR: HID required\n", dev_path(dev)); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/44001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f6a38aac6e7f94c3c370996b3b82ca0d88dac4 Gerrit-Change-Number: 44001 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/volteer/var/terrador: Support ELAN i2c-hid touchpad
by David Wu (Code Review) 03 Aug '20

03 Aug '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43998 ) Change subject: mb/google/volteer/var/terrador: Support ELAN i2c-hid touchpad ...................................................................... mb/google/volteer/var/terrador: Support ELAN i2c-hid touchpad Update ELAN i2c-hid touchpad configuration BUG=b:160741785 BRANCH=None TEST=Verify touchpad is working fine. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I2549048766d0707666910bd86c46ac9201bf3905 --- M src/mainboard/google/volteer/variants/todor/overridetree.cb 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/43998/1 diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index c1c386a..8c0fb38 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -117,12 +117,13 @@ end end # I2C2 0xA0EA device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" - register "wake" = "GPE0_DW2_15" - register "probed" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2700"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end end # I2C5 0xA0C6 -- To view, visit https://review.coreboot.org/c/coreboot/+/43998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2549048766d0707666910bd86c46ac9201bf3905 Gerrit-Change-Number: 43998 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/zork: Add Samsung Samsung K4AAG165WA-BCTD SPD
by Kevin Chiu (Code Review) 03 Aug '20

03 Aug '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43990 ) Change subject: mb/google/zork: Add Samsung Samsung K4AAG165WA-BCTD SPD ...................................................................... mb/google/zork: Add Samsung Samsung K4AAG165WA-BCTD SPD For dirinboz DRAMID 0x9: H5AN8G6NDJR-XNC BUG=b:161579679 BRANCH=master TEST=build Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293 --- A src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCTD.spd.hex 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/43990/1 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCTD.spd.hex new file mode 100644 index 0000000..71b05a2 --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WA-BCWE +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/43990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293 Gerrit-Change-Number: 43990 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/tigerlake: Invoke PCIe root port swapping
by Patrick Georgi (Code Review) 03 Aug '20

03 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43850 ) Change subject: soc/intel/tigerlake: Invoke PCIe root port swapping ...................................................................... soc/intel/tigerlake: Invoke PCIe root port swapping PCIe bus:function specifiers need to be coalesced the same way functions are coalesced during bus enumeration. Invoke PCIe root port devicetree update to swap the enabled root port devices with the disabled devices. At this point, the TGL pci_devs.h only describes the PCH-LP, so only the PCH-LP root ports are listed in this patch. We'll need to add additional PCIe root ports when PCH-H support is added. BUG=b:162106164 TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is swapped with the PCIe device 1c.0 corresponding to Root port 1. Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/tigerlake/chip.c 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index d08355e..d3c3c62 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -8,6 +8,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> @@ -16,6 +17,12 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -140,6 +147,9 @@ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); soc_fill_gpio_pm_configuration(); + + /* Swap enabled PCI ports in device tree if needed. */ + pcie_rp_update_devicetree(pch_lp_rp_groups); } static struct device_operations pci_domain_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62 Gerrit-Change-Number: 43850 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: lenovo/x230: introduce FHD variant
by slact (Code Review) 03 Aug '20

03 Aug '20

slact has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 12: I'm seeing an issue where zero-brightness (Backlight off) is being treated as full brightness. So instead of turning off the backlight when the lid is closed, it's set to max. Tested with patchset 12 on master @ e2f5fb25 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 12 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kilian Neuner <cb(a)9-r.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-CC: slact Gerrit-Comment-Date: Mon, 03 Aug 2020 04:02:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/mipi_camera: Add reference counting for shared resources
by Subrata Banik (Code Review) 03 Aug '20

03 Aug '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43003 ) Change subject: drivers/intel/mipi_camera: Add reference counting for shared resources ...................................................................... drivers/intel/mipi_camera: Add reference counting for shared resources This change updates the mipi_camera driver to handle shared power resource between multiple cameras. This is achieved by adding a guard variable and methods to manipulate the guard variable before calling the actual platform method which enables or disables the resource. PowerResource will call these guarded methods to enable or disable the resource. This protects the shared resource from being enabled or disabled multiple times while the other camera is using the resource. Example: Consider a platform where two cameras are sharing a GPIO resource 0xXX and both the cameras calls enable and disable guarded methods for this GPIO. Actual platform disable method for the GPIO is called only after the last camera using the GPIO calls DSBx method and RESx becomes 0. Scope (\_SB.PCI0) { Name (RESx, Zero) Method (ENBx, 0, Serialized) { If ((RESx == Zero)) { \_SB.PCI0.STXS (0xXX) } RESx++ } Method (DSBx, 0, Serialized) { If ((RESx > Zero)) { RESx-- } If ((RESx == Zero)) { \_SB.PCI0.CTXS (0xXX) } } } Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43003 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 353 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index f32f744..51686d0 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -18,6 +18,59 @@ #define CIO2_PCI_DEV 0x14 #define CIO2_PCI_FN 0x3 #define POWER_RESOURCE_NAME "PRIC" +#define GUARD_VARIABLE_FORMAT "RES%1d" +#define ENABLE_METHOD_FORMAT "ENB%1d" +#define DISABLE_METHOD_FORMAT "DSB%1d" +#define UNKNOWN_METHOD_FORMAT "UNK%1d" +#define CLK_ENABLE_METHOD "MCON" +#define CLK_DISABLE_METHOD "MCOF" + +static struct camera_resource_manager res_mgr; + +static void resource_set_action_type(struct resource_config *res_config, + enum action_type action) +{ + if (res_config) + res_config->action = action; +} + +static enum action_type resource_get_action_type(const struct resource_config *res_config) +{ + return res_config ? res_config->action : UNKNOWN_ACTION; +} + +static enum ctrl_type resource_get_ctrl_type(const struct resource_config *res_config) +{ + return res_config ? res_config->type : UNKNOWN_CTRL; +} + +static void resource_set_clk_config(struct resource_config *res_config, + const struct clk_config *clk_conf) +{ + if (res_config) { + res_config->type = IMGCLK; + res_config->clk_conf = clk_conf; + } +} + +static const struct clk_config *resource_clk_config(const struct resource_config *res_config) +{ + return res_config ? res_config->clk_conf : NULL; +} + +static void resource_set_gpio_config(struct resource_config *res_config, + const struct gpio_config *gpio_conf) +{ + if (res_config) { + res_config->type = GPIO; + res_config->gpio_conf = gpio_conf; + } +} + +static const struct gpio_config *resource_gpio_config(const struct resource_config *res_config) +{ + return res_config ? res_config->gpio_conf : NULL; +} /* * This implementation assumes there is only 1 endpoint at each end of every data port. It also @@ -436,53 +489,271 @@ acpi_dp_write(dsd); } -static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *config, - struct operation_seq *seq) +static int get_resource_index(const struct resource_config *res_config) +{ + enum ctrl_type type = resource_get_ctrl_type(res_config); + const struct clk_config *clk_config; + const struct gpio_config *gpio_config; + unsigned int i; + uint8_t res_id; + + switch (type) { + case IMGCLK: + clk_config = resource_clk_config(res_config); + res_id = clk_config->clknum; + break; + case GPIO: + gpio_config = resource_gpio_config(res_config); + res_id = gpio_config->gpio_num; + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work", type); + return -1; + } + + for (i = 0; i < res_mgr.cnt; i++) + if (res_mgr.resource[i].type == type && res_mgr.resource[i].id == res_id) + return i; + + return -1; +} + +static void add_guarded_method_namestring(struct resource_config *res_config, int res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + enum action_type action = resource_get_action_type(res_config); + + switch (action) { + case ENABLE: + snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, res_index); + break; + case DISABLE: + snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, res_index); + break; + default: + snprintf(method_name, sizeof(method_name), UNKNOWN_METHOD_FORMAT, res_index); + printk(BIOS_ERR, "Unsupported resource action: %x\n", action); + } + + acpigen_emit_namestring(method_name); +} + +static void call_guarded_method(struct resource_config *res_config) +{ + int res_index; + + if (res_config == NULL) + return; + + res_index = get_resource_index(res_config); + + if (res_index != -1) + add_guarded_method_namestring(res_config, res_index); +} + +static void add_clk_op(const struct clk_config *clk_config, enum action_type action) +{ + if (clk_config == NULL) + return; + + switch (action) { + case ENABLE: + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_string(CLK_ENABLE_METHOD); + acpigen_emit_namestring(CLK_ENABLE_METHOD); + acpigen_write_integer(clk_config->clknum); + acpigen_write_integer(clk_config->freq); + acpigen_pop_len(); /* CondRefOf */ + break; + case DISABLE: + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_string(CLK_DISABLE_METHOD); + acpigen_emit_namestring(CLK_DISABLE_METHOD); + acpigen_write_integer(clk_config->clknum); + acpigen_pop_len(); /* CondRefOf */ + break; + default: + acpigen_write_debug_string("Unsupported clock action"); + printk(BIOS_ERR, "Unsupported clock action: %x\n" + "OS camera driver will likely not work", action); + } +} + +static void add_gpio_op(const struct gpio_config *gpio_config, enum action_type action) +{ + if (gpio_config == NULL) + return; + + switch (action) { + case ENABLE: + acpigen_soc_set_tx_gpio(gpio_config->gpio_num); + break; + case DISABLE: + acpigen_soc_clear_tx_gpio(gpio_config->gpio_num); + break; + default: + acpigen_write_debug_string("Unsupported GPIO action"); + printk(BIOS_ERR, "Unsupported GPIO action: %x\n" + "OS camera driver will likely not work\n", action); + } +} + +static void add_power_operation(const struct resource_config *res_config) +{ + const struct clk_config *clk_config; + const struct gpio_config *gpio_config; + enum ctrl_type type = resource_get_ctrl_type(res_config); + enum action_type action = resource_get_action_type(res_config); + + if (res_config == NULL) + return; + + switch (type) { + case IMGCLK: + clk_config = resource_clk_config(res_config); + add_clk_op(clk_config, action); + break; + case GPIO: + gpio_config = resource_gpio_config(res_config); + add_gpio_op(gpio_config, action); + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", type); + break; + } +} + +static void write_guard_variable(uint8_t res_index) +{ + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + acpigen_write_name_integer(varname, 0); +} + +static void write_enable_method(struct resource_config *res_config, uint8_t res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + + snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, res_index); + + acpigen_write_method_serialized(method_name, 0); + acpigen_write_if_lequal_namestr_int(varname, 0); + resource_set_action_type(res_config, ENABLE); + add_power_operation(res_config); + acpigen_pop_len(); /* if */ + + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(varname); + acpigen_pop_len(); /* method_name */ +} + +static void write_disable_method(struct resource_config *res_config, uint8_t res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + + snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, res_index); + + acpigen_write_method_serialized(method_name, 0); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_namestring(varname); + acpigen_write_integer(0x0); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring(varname); + acpigen_pop_len(); /* if */ + + acpigen_write_if_lequal_namestr_int(varname, 0); + resource_set_action_type(res_config, DISABLE); + add_power_operation(res_config); + acpigen_pop_len(); /* if */ + acpigen_pop_len(); /* method_name */ +} + +static void add_guarded_operations(const struct drivers_intel_mipi_camera_config *config, + const struct operation_seq *seq) { unsigned int i; uint8_t index; - uint8_t gpio_num; + uint8_t res_id; + struct resource_config res_config; + int res_index; - for (i = 0; i < seq->ops_cnt; i++) { + for (i = 0; i < seq->ops_cnt && i < MAX_PWR_OPS; i++) { + index = seq->ops[i].index; switch (seq->ops[i].type) { case IMGCLK: - index = seq->ops[i].index; - if (seq->ops[i].action == ENABLE) { - acpigen_emit_namestring("MCON"); - acpigen_write_byte(config->clk_panel.clks[index].clknum); - acpigen_write_byte(config->clk_panel.clks[index].freq); - } else if (seq->ops[i].action == DISABLE) { - acpigen_emit_namestring("MCOF"); - acpigen_write_byte(config->clk_panel.clks[index].clknum); - } else { - acpigen_write_debug_string("Unsupported clock action"); - printk(BIOS_ERR, "Unsupported clock action: %x\n", - seq->ops[i].action); - printk(BIOS_ERR, "OS camera driver will likely not work"); - } - + res_id = config->clk_panel.clks[index].clknum; + resource_set_clk_config(&res_config, &config->clk_panel.clks[index]); break; case GPIO: - index = seq->ops[i].index; - gpio_num = config->gpio_panel.gpio[index].gpio_num; - if (seq->ops[i].action == ENABLE) { - acpigen_soc_set_tx_gpio(gpio_num); - } else if (seq->ops[i].action == DISABLE) { - acpigen_soc_clear_tx_gpio(gpio_num); - } else { - acpigen_write_debug_string("Unsupported GPIO action"); - printk(BIOS_ERR, "Unsupported GPIO action: %x\n", - seq->ops[i].action); - printk(BIOS_ERR, "OS camera driver will likely not work"); - } - + res_id = config->gpio_panel.gpio[index].gpio_num; + resource_set_gpio_config(&res_config, &config->gpio_panel.gpio[index]); break; default: - printk(BIOS_ERR, "Unsupported power operation: %x\n", seq->ops[i].type); - printk(BIOS_ERR, "OS camera driver will likely not work"); - break; + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", + seq->ops[i].type); + return; } + res_index = get_resource_index(&res_config); + + if (res_index == -1) { + if (res_mgr.cnt >= MAX_GUARDED_RESOURCES) { + printk(BIOS_ERR, "Unable to add guarded camera resource\n" + "OS camera driver will likely not work\n"); + return; + } + + res_mgr.resource[res_mgr.cnt].id = res_id; + res_mgr.resource[res_mgr.cnt].type = seq->ops[i].type; + + write_guard_variable(res_mgr.cnt); + write_enable_method(&res_config, res_mgr.cnt); + write_disable_method(&res_config, res_mgr.cnt); + + res_mgr.cnt++; + } + } +} + +static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *config, + struct operation_seq *seq) +{ + struct resource_config res_config; + unsigned int i; + uint8_t index; + + for (i = 0; i < seq->ops_cnt && i < MAX_PWR_OPS; i++) { + index = seq->ops[i].index; + + switch (seq->ops[i].type) { + case IMGCLK: + resource_set_clk_config(&res_config, &config->clk_panel.clks[index]); + break; + case GPIO: + resource_set_gpio_config(&res_config, &config->gpio_panel.gpio[index]); + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", + seq->ops[i].type); + return; + } + + resource_set_action_type(&res_config, seq->ops[i].action); + call_guarded_method(&res_config); if (seq->ops[i].delay_ms) acpigen_write_sleep(seq->ops[i].delay_ms); } @@ -638,12 +909,32 @@ static void camera_fill_ssdt(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); + const char *scope = NULL; + const struct device *pdev; - if (!dev->enabled || !scope) + if (!dev->enabled) return; + if (config->has_power_resource) { + pdev = dev->bus->dev; + if (!pdev || !pdev->enabled) + return; + + scope = acpi_device_scope(pdev); + if (!scope) + return; + + acpigen_write_scope(scope); + add_guarded_operations(config, &config->on_seq); + add_guarded_operations(config, &config->off_seq); + acpigen_pop_len(); /* Guarded power resource operations scope */ + } + /* Device */ + scope = acpi_device_scope(dev); + if (!scope) + return; + acpigen_write_scope(scope); if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || @@ -669,7 +960,7 @@ static const char *camera_acpi_name(const struct device *dev) { const char *prefix = NULL; - static char name[5]; + static char name[ACPI_NAME_BUFFER_SIZE]; struct drivers_intel_mipi_camera_config *config = dev->chip_info; if (config->acpi_name) diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index d133f7d..d91e1e7 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -13,6 +13,7 @@ #define MAX_CLK_CONFIGS 2 #define MAX_GPIO_CONFIGS 4 #define MAX_PWR_OPS 5 +#define MAX_GUARDED_RESOURCES 10 #define SEQ_OPS_CLK_ENABLE(ind, delay) \ { .type = IMGCLK, .index = (ind), .action = ENABLE, .delay_ms = (delay) } @@ -70,15 +71,36 @@ }; enum ctrl_type { - IMGCLK = 1, + UNKNOWN_CTRL, + IMGCLK, GPIO }; enum action_type { - ENABLE = 1, + UNKNOWN_ACTION, + ENABLE, DISABLE }; +struct camera_resource { + uint8_t type; + uint8_t id; +}; + +struct camera_resource_manager { + uint8_t cnt; + struct camera_resource resource[MAX_GUARDED_RESOURCES]; +}; + +struct resource_config { + enum action_type action; + enum ctrl_type type; + union { + const struct clk_config *clk_conf; + const struct gpio_config *gpio_conf; + }; +}; + struct clk_config { /* IMGCLKOUT_x being used for a port */ uint8_t clknum; -- To view, visit https://review.coreboot.org/c/coreboot/+/43003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Gerrit-Change-Number: 43003 Gerrit-PatchSet: 14 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
by Felix Held (Code Review) 02 Aug '20

02 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44069 ) Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ...................................................................... vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments Also document the maximum nuber of lanes for the different platforms. Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44069/1 diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 9c0e3e9..12e52fc 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -123,7 +123,16 @@ * GPP[5:4] | [1:0] | PCIe, XGBE * GPP[7:6] | [3:2] | PCIe, SATA * - * Dali has less DXIO connectivity than Picasso: + * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port + * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1 + * ports. The ports can only start at logical lane numbers that are integer multiples of the + * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12. + * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the + * same width the one with a higher start logical lane number needs to be assigned to a higher + * PCIe root port number; ports of the same size don't have to be assigned to continious PCIe + * root ports though. + * + * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso: * * physical | logical | protocol * ---------|---------|----------- -- To view, visit https://review.coreboot.org/c/coreboot/+/44069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Gerrit-Change-Number: 44069 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 5

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2020