Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39581 )
Change subject: src/soc/intel/tigerlake: Update SD card ACPI device
......................................................................
src/soc/intel/tigerlake: Update SD card ACPI device
1. Add _DSM method
2. Add support to turn on/off the power enable
signal in _PS0/_PS3 methods.
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9
---
M src/soc/intel/tigerlake/acpi/scs.asl
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
2 files changed, 72 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/39581/1
diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl
index a9ff93c..6b391a8 100644
--- a/src/soc/intel/tigerlake/acpi/scs.asl
+++ b/src/soc/intel/tigerlake/acpi/scs.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -84,6 +84,7 @@
Name (_ADR, 0x00140005)
Name (_DDN, "SD Controller")
Name (TEMP, 0)
+ Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))
OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
Field (SDPC, WordAcc, NoLock, Preserve)
@@ -95,6 +96,63 @@
PGEN, 1, /* PG_ENABLE */
}
+ /* _DSM x86 Device Specific Method
+ * Arg0: UUID Unique function identifier
+ * Arg1: Integer Revision Level
+ * Arg2: Integer Function Index (0 = Return Supported Functions)
+ * Arg3: Package Parameters
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, DSUU)) {
+ /* Check the revision */
+ If (LGreaterEqual (Arg1, Zero)) {
+ /*
+ * Function Index 0 the return value is a buffer containing
+ * one bit for each function index, starting with zero.
+ * Bit 0 - Indicates whether there is support for any functions other than function 0.
+ * Bit 1 - Indicates support to clear power control register
+ * Bit 2 - Indicates support to set power control register
+ * Bit 3 - Indicates support to set 1.8V signalling
+ * Bit 4 - Indicates support to set 3.3V signalling
+ * Bit 5 - Indicates support for HS200 mode
+ * Bit 6 - Indicates support for HS400 mode
+ * Bit 9 - Indicates eMMC I/O Driver Strength
+ */
+ /*
+ * For SD we have to support functions to
+ * set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
+ */
+ If (LEqual (Arg2, Zero)) {
+ Return (Buffer () { 0x19 })
+ }
+ /*
+ * Function Index 3: Set 1.8v signalling.
+ * We put a sleep of 100ms in this method to
+ * work around a known issue with detecting
+ * UHS SD card on PCH. This is to compensate
+ * for the SD VR slowness.
+ */
+ If (LEqual (Arg2, 3)) {
+ Sleep (100)
+ Return(Buffer () { 0x00 })
+ }
+ /*
+ * Function Index 4: Set 3.3v signalling.
+ * We put a sleep of 100ms in this method to
+ * work around a known issue with detecting
+ * UHS SD card on PCH. This is to compensate
+ * for the SD VR slowness.
+ */
+ If (LEqual (Arg2, 4)) {
+ Sleep (100)
+ Return(Buffer () { 0x00 })
+ }
+ }
+ }
+ Return(Buffer() { 0x0 })
+ }
+
Method(_INI)
{
/* Clear register 0x1C20/0x4820 */
@@ -111,6 +169,9 @@
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, TEMP)
+
+ /* Change pad mode to Native */
+ GPMO(SD_PWR_EN_PIN, 0x1)
}
Method (_PS3, 0, Serialized)
@@ -120,6 +181,15 @@
/* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR)
Store (PMCR, TEMP)
+
+ /* Change pad mode to GPIO control */
+ GPMO(SD_PWR_EN_PIN, 0x0)
+
+ /* Enable Tx Buffer */
+ GTXE(SD_PWR_EN_PIN, 0x1)
+
+ /* Drive TX to zero */
+ CTXS(SD_PWR_EN_PIN)
}
Device (CARD)
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
index ce7d0d8..05e5696 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
@@ -37,7 +37,7 @@
#define GPIO_NUM_GROUPS 11
#define GPIO_MAX_NUM_PER_GROUP 24
-
+#define SD_PWR_EN_PIN GPP_H1
/*
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
*/
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9
Gerrit-Change-Number: 39581
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange