coreboot-gerrit August 2020

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Change in coreboot[master]: mb/google/dedede: Update CPU critical temperature
by Sumeet R Pawnikar (Code Review) 03 Aug '20

03 Aug '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44054 ) Change subject: mb/google/dedede: Update CPU critical temperature ...................................................................... mb/google/dedede: Update CPU critical temperature Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with heavy workload like WebGL Aquarium, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. This updates CPU critical temperature trip value to 105 degree Celsius to avoid system shutdown. BUG=None BRANCH=None TEST=Built and tested on dedede system Change-Id: If15a873a997aa80f20940f27bbafd4498908c091 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44054/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7502489..d0609ef 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -175,7 +175,7 @@ register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 99, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" -- To view, visit https://review.coreboot.org/c/coreboot/+/44054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15a873a997aa80f20940f27bbafd4498908c091 Gerrit-Change-Number: 44054 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR support
by Duan huayang (Code Review) 03 Aug '20

03 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44011 ) Change subject: UPSTREAM: mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR support ...................................................................... UPSTREAM: mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR support Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup. BUG=b:159301679 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c 3 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44011/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 7638853..5bf6571 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -20,6 +20,7 @@ [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", [8] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [9] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", [10] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", #endif }; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 2b43519..e8dc639 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -14,6 +14,7 @@ sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB + sdram-params += sdram-lpddr4x-MT53E2G32D4NQ-046-8GB endif $(foreach params,$(sdram-params), \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c new file mode 100644 index 0000000..81887b5 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/emi.h> + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353 Gerrit-Change-Number: 44011 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ocp/ipmi: Add ipmi set processor information
by Tim Chu (Code Review) 03 Aug '20

03 Aug '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42242 ) Change subject: drivers/ocp/ipmi: Add ipmi set processor information ...................................................................... drivers/ocp/ipmi: Add ipmi set processor information Implement setting processor information to BMC. TEST=Use get command in OpenBMC to check. Command and information are shown as below: root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 1 DC 11 00 47 65 6E 75 69 6E 65 20 49 6E 74 65 6C 28 52 29 20 43 50 55 20 30 30 30 30 25 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 2 DC 11 00 1A 34 00 DC 05 58 58 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu(a)quantatw.com> Change-Id: I3d53ac241a11ca962572816283a0c653fcde9f9e --- M src/drivers/ocp/ipmi/Kconfig M src/drivers/ocp/ipmi/ipmi_ocp.c M src/drivers/ocp/ipmi/ipmi_ocp.h 3 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42242/1 diff --git a/src/drivers/ocp/ipmi/Kconfig b/src/drivers/ocp/ipmi/Kconfig index 95c51c0..d4ebafe 100644 --- a/src/drivers/ocp/ipmi/Kconfig +++ b/src/drivers/ocp/ipmi/Kconfig @@ -1,3 +1,8 @@ config IPMI_OCP bool default n + +config MANU_ID + hex + default 0 + depends on IPMI_OCP diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.c b/src/drivers/ocp/ipmi/ipmi_ocp.c index c1766d9..4ad710d 100644 --- a/src/drivers/ocp/ipmi/ipmi_ocp.c +++ b/src/drivers/ocp/ipmi/ipmi_ocp.c @@ -54,6 +54,108 @@ return 0; } +static int ipmi_set_processor_information_param1(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param1_req req1 = {0}; + struct ipmi_rsp rsp; + + for (int index = 0; index < sizeof(req1.data.manufacturer_id); index++) { + req1.data.manufacturer_id[index] = (mfid >> (index * 8)) & 0xff; + } + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req1.data.manufacturer_id[2], req1.data.manufacturer_id[1], + req1.data.manufacturer_id[0]); + + req1.data.index = 0; + req1.data.parameter_selector = 1; + + /* Get processor name. */ + fill_processor_name(req1.product_name); + printk(BIOS_DEBUG, "IPMI CPU NAME: %s.\n", req1.product_name); + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req1, + sizeof(req1), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI BMC: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static int ipmi_set_processor_information_param2(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param2_req req2 = {0}; + struct ipmi_rsp rsp; + struct cpuid_result regs; + msr_t msr; + uint8_t stepping_id; + + for (int index = 0; index < sizeof(req2.data.manufacturer_id); index++) { + req2.data.manufacturer_id[index] = (mfid >> (index * 8)) & 0xff; + } + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req2.data.manufacturer_id[2], req2.data.manufacturer_id[1], + req2.data.manufacturer_id[0]); + + req2.data.index = 0; + req2.data.parameter_selector = 2; + + /* Get core number and thread number. */ + msr = rdmsr(MSR_CORE_THREAD_COUNT); + req2.thread_number = (msr.lo >> 0) & 0xffff; + req2.core_number = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "IPMI CPU has %u cores, %u threads enabled.\n", + req2.core_number, req2.thread_number); + + /* Get processor frequency. */ + msr = rdmsr(MSR_PLATFORM_INFO); + req2.processor_freq = 100 * ((msr.lo >> 8) & 0xff); + printk(BIOS_DEBUG, "IPMI CPU frequency is %u MHz.\n", + req2.processor_freq); + + /* Get revision. */ + regs = cpuid(0x01); + stepping_id = (regs.eax & 0xf); + printk(BIOS_DEBUG, "IPMI CPU stepping id is %x.\n", stepping_id); + switch (stepping_id) { + /* TBD */ + case 0xa: + req2.revision[0] = 'X'; + req2.revision[1] = 'X'; + break; + default: + req2.revision[0] = 'X'; + req2.revision[1] = 'X'; + } + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req2, + sizeof(req2), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static void ipmi_set_processor_information(struct device *dev) +{ + if (ipmi_set_processor_information_param1(dev)) { + printk(BIOS_ERR, "IPMI BMC set param 1 processor info failed\n"); + } + + if (ipmi_set_processor_information_param2(dev)) { + printk(BIOS_ERR, "IPMI BMC set param 2 processor info failed\n"); + } +} + static void ipmi_ocp_init(struct device *dev) { struct ipmi_rsp postrsp; @@ -67,6 +169,9 @@ { struct ipmi_rsp postrsp; + /* Send processor information */ + ipmi_set_processor_information(dev); + /* Send POST end to BMC. */ if (!ipmi_set_post_end(dev, &postrsp)) printk(BIOS_DEBUG, "IPMI BMC POST is ended\n"); diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.h b/src/drivers/ocp/ipmi/ipmi_ocp.h index 1cdea2f..f04b5ba 100644 --- a/src/drivers/ocp/ipmi/ipmi_ocp.h +++ b/src/drivers/ocp/ipmi/ipmi_ocp.h @@ -3,8 +3,36 @@ #ifndef __IPMI_OCP_H #define __IPMI_OCP_H +#include <soc/msr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/name.h> +#include "drivers/ipmi/ipmi_kcs.h" #define IPMI_NETFN_OEM 0x30 #define IPMI_BMC_SET_POST_START 0x73 #define IPMI_BMC_SET_POST_END 0x74 +#define IPMI_NETFN_OEM_COMMON 0x36 +#define IPMI_BMC_SET_PROCESSOR_INFORMATION 0x10 +#define IPMI_BMC_GET_PROCESSOR_INFORMATION 0x11 + +#define mfid CONFIG_MANU_ID + +struct ipmi_processor_info_req { + uint8_t manufacturer_id[3]; + uint8_t index; + uint8_t parameter_selector; +} __packed; + +struct ipmi_processor_info_param1_req { + struct ipmi_processor_info_req data; + char product_name[48]; +} __packed; + +struct ipmi_processor_info_param2_req { + struct ipmi_processor_info_req data; + uint8_t core_number; + uint16_t thread_number; + uint16_t processor_freq; + char revision[2]; +} __packed; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d53ac241a11ca962572816283a0c653fcde9f9e Gerrit-Change-Number: 42242 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/cedarisland: Remove duplicated code
by Patrick Georgi (Code Review) 03 Aug '20

03 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43924 ) Change subject: mb/intel/cedarisland: Remove duplicated code ...................................................................... mb/intel/cedarisland: Remove duplicated code Some UPD options are already set in `xeon_sp/cpx/romstage.c`. Remove them from the board configuration to avoid duplicating this code. Change-Id: Ic79245103c33427e06c7ea881be778e3d219c45f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43924 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/cedarisland_crb/romstage.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index 8468605..03e28a1 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -6,9 +6,5 @@ { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->BoardId = 0x1d; - m_cfg->BoardTypeBitmask = 0x11111111; - m_cfg->DebugPrintLevel = 8; m_cfg->KtiLinkSpeedMode = 0; - m_cfg->KtiPrefetchEn = 2; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic79245103c33427e06c7ea881be778e3d219c45f Gerrit-Change-Number: 43924 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD
by Patrick Georgi (Code Review) 03 Aug '20

03 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43923 ) Change subject: mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD ...................................................................... mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h, use FSP_M_CONFIG structure fields to configure UPD options for FSP-M in romstage instead of raw offsets. Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/cedarisland_crb/romstage.c 1 file changed, 5 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index e82d26b..8468605 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,25 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - void *start = (void *) m_cfg; - // BoardId - write8(start + 140, 0x1d); - - // BoardTypeBitmask - write32(start + 104, 0x11111111); - - // DebugPrintLevel - write8(start + 45, 8); - - // KtiLinkSpeedMode - write8(start + 64, 0); - - // KtiPrefetchEn - write8(start + 53, 2); + m_cfg->BoardId = 0x1d; + m_cfg->BoardTypeBitmask = 0x11111111; + m_cfg->DebugPrintLevel = 8; + m_cfg->KtiLinkSpeedMode = 0; + m_cfg->KtiPrefetchEn = 2; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a Gerrit-Change-Number: 43923 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/madoo: Add discrete WiFi configuration
by Dtrain Hsu (Code Review) 03 Aug '20

03 Aug '20

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44056 ) Change subject: mb/google/dedede/var/madoo: Add discrete WiFi configuration ...................................................................... mb/google/dedede/var/madoo: Add discrete WiFi configuration Add RTL8822CE support for Madoo. BUG=b:162390420 BRANCH=None TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6 --- M src/mainboard/google/dedede/variants/madoo/overridetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/44056/1 diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 3f99927..6937338 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -91,7 +91,13 @@ end end # I2C 2 device pci 15.3 off end # I2C 3 - device pci 1c.7 on end + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + register "maxsleep" = "3" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/44056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6 Gerrit-Change-Number: 44056 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C p...
by Dtrain Hsu (Code Review) 03 Aug '20

03 Aug '20

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44052 ) Change subject: mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C ports ...................................................................... mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C ports 1. Add Elan touchpad support. 2. Follow schematic to disable I2C1 and I2C3. BUG=b:160869188,b:161407664 BRANCH=NONE TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616 --- M src/mainboard/google/dedede/variants/madoo/gpio.c M src/mainboard/google/dedede/variants/madoo/overridetree.cb 2 files changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44052/1 diff --git a/src/mainboard/google/dedede/variants/madoo/gpio.c b/src/mainboard/google/dedede/variants/madoo/gpio.c index f9f8ea2..314d39e 100644 --- a/src/mainboard/google/dedede/variants/madoo/gpio.c +++ b/src/mainboard/google/dedede/variants/madoo/gpio.c @@ -5,6 +5,10 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), /* D12 : WCAM_RST_L */ PAD_NC(GPP_D12, NONE), /* D13 : EN_PP2800_CAMERA */ diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index f8e2b06..3f99927 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -6,6 +6,15 @@ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not Used + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -15,7 +24,7 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | | #| I2C2 | Touchscreen | #| I2C3 | | #| I2C4 | Audio | @@ -28,9 +37,6 @@ .i2c[0] = { .speed = I2C_SPEED_FAST, }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, @@ -56,7 +62,17 @@ end end end # USB xHCI - device pci 15.0 on end + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.1 off end # I2C 1 device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" @@ -74,6 +90,7 @@ device i2c 0x5d on end end end # I2C 2 + device pci 15.3 off end # I2C 3 device pci 1c.7 on end device pci 19.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/44052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616 Gerrit-Change-Number: 44052 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/madoo: Enable Goodix touchscreen
by Ian Feng (Code Review) 03 Aug '20

03 Aug '20

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44012 ) Change subject: mb/google/dedede/var/madoo: Enable Goodix touchscreen ...................................................................... mb/google/dedede/var/madoo: Enable Goodix touchscreen Add Goodix touchscreen support. BUG=b:160868197 TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23 --- M src/mainboard/google/dedede/variants/madoo/overridetree.cb 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44012/1 diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index e189ec3..f8e2b06 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -57,7 +57,23 @@ end end # USB xHCI device pci 15.0 on end - device pci 15.2 on end + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 device pci 1c.7 on end device pci 19.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/44012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23 Gerrit-Change-Number: 44012 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/tigerlake: Update SD card ACPI device
by Aamir Bohra (Code Review) 03 Aug '20

03 Aug '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39581 ) Change subject: src/soc/intel/tigerlake: Update SD card ACPI device ...................................................................... src/soc/intel/tigerlake: Update SD card ACPI device 1. Add _DSM method 2. Add support to turn on/off the power enable signal in _PS0/_PS3 methods. Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9 --- M src/soc/intel/tigerlake/acpi/scs.asl M src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h 2 files changed, 72 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/39581/1 diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl index a9ff93c..6b391a8 100644 --- a/src/soc/intel/tigerlake/acpi/scs.asl +++ b/src/soc/intel/tigerlake/acpi/scs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -84,6 +84,7 @@ Name (_ADR, 0x00140005) Name (_DDN, "SD Controller") Name (TEMP, 0) + Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61")) OperationRegion (SDPC, PCI_Config, 0x00, 0x100) Field (SDPC, WordAcc, NoLock, Preserve) @@ -95,6 +96,63 @@ PGEN, 1, /* PG_ENABLE */ } + /* _DSM x86 Device Specific Method + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, DSUU)) { + /* Check the revision */ + If (LGreaterEqual (Arg1, Zero)) { + /* + * Function Index 0 the return value is a buffer containing + * one bit for each function index, starting with zero. + * Bit 0 - Indicates whether there is support for any functions other than function 0. + * Bit 1 - Indicates support to clear power control register + * Bit 2 - Indicates support to set power control register + * Bit 3 - Indicates support to set 1.8V signalling + * Bit 4 - Indicates support to set 3.3V signalling + * Bit 5 - Indicates support for HS200 mode + * Bit 6 - Indicates support for HS400 mode + * Bit 9 - Indicates eMMC I/O Driver Strength + */ + /* + * For SD we have to support functions to + * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] + */ + If (LEqual (Arg2, Zero)) { + Return (Buffer () { 0x19 }) + } + /* + * Function Index 3: Set 1.8v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (LEqual (Arg2, 3)) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + /* + * Function Index 4: Set 3.3v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (LEqual (Arg2, 4)) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + } + } + Return(Buffer() { 0x0 }) + } + Method(_INI) { /* Clear register 0x1C20/0x4820 */ @@ -111,6 +169,9 @@ /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, TEMP) + + /* Change pad mode to Native */ + GPMO(SD_PWR_EN_PIN, 0x1) } Method (_PS3, 0, Serialized) @@ -120,6 +181,15 @@ /* Set Power State to D3 */ Or (PMCR, 0x0003, PMCR) Store (PMCR, TEMP) + + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Enable Tx Buffer */ + GTXE(SD_PWR_EN_PIN, 0x1) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) } Device (CARD) diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h index ce7d0d8..05e5696 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h @@ -37,7 +37,7 @@ #define GPIO_NUM_GROUPS 11 #define GPIO_MAX_NUM_PER_GROUP 24 - +#define SD_PWR_EN_PIN GPP_H1 /* * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9 Gerrit-Change-Number: 39581 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/up/squared: rewrite GPIO config using intelp2m
by Maxim Polyakov (Code Review) 03 Aug '20

03 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39765 ) Change subject: mb/up/squared: rewrite GPIO config using intelp2m ...................................................................... mb/up/squared: rewrite GPIO config using intelp2m This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. This configuration was generated using the Intel Pad 2 Macro utility (intelp2m / pch-pads-parser) [1,2]. [1] https: //github.com/maxpoliak/pch-pads-parser [2] https: //review.coreboot.org/c/coreboot/+/35643 [WIP] Please review and test coreboot image with this patch Change-Id: I266ec6fa10a9691a7b7d3cd6f2792624e8bd53d5 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/up/squared/gpio.h 1 file changed, 257 insertions(+), 745 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39765/1 diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 52a67ee..af69cf7 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -18,755 +18,267 @@ #define GPIO_H static const struct pad_config gpio_table[] = { - // ******************************** - // ******* GPIO Group North ******* - // ******************************** - // *GPIO - _PAD_CFG_STRUCT(GPIO_0, 0x04000102, 0x00000000), - // *GPIO - _PAD_CFG_STRUCT(GPIO_1, 0x04000102, 0x00000000), + /* ******* GPIO Group North ******* */ + PAD_CFG_GPI_INT(GPIO_0, NONE, PWROK, OFF), + PAD_CFG_GPI_INT(GPIO_1, NONE, PWROK, OFF), + PAD_CFG_GPI_INT(GPIO_2, NONE, PWROK, OFF), + PAD_CFG_GPI_INT(GPIO_3, NONE, PWROK, OFF), + PAD_CFG_GPI_INT(GPIO_4, NONE, PWROK, OFF), + PAD_CFG_GPI_INT(GPIO_5, NONE, DEEP, OFF), + PAD_CFG_GPO(GPIO_6, 1, DEEP), + PAD_CFG_GPO(GPIO_7, 1, DEEP), + PAD_CFG_GPO(GPIO_8, 1, DEEP), + PAD_CFG_GPO(GPIO_9, 1, DEEP), + PAD_CFG_GPO(GPIO_10, 1, DEEP), + PAD_CFG_GPO(GPIO_11, 1, DEEP), + PAD_CFG_GPO(GPIO_12, 1, DEEP), + PAD_CFG_GPI_INT(GPIO_13, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_14, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_15, NONE, DEEP, OFF), + PAD_CFG_GPI_SCI_IOS(GPIO_16, NONE, DEEP, LEVEL, YES, TxDRxE, SAME), + PAD_CFG_GPO(GPIO_17, 1, DEEP), + PAD_CFG_GPO(GPIO_18, 1, DEEP), + PAD_CFG_TERM_GPO(GPIO_19, 1, 20K_PU, DEEP), + PAD_CFG_GPI_INT(GPIO_20, NONE, DEEP, OFF), + PAD_CFG_GPO(GPIO_21, 1, DEEP), + PAD_CFG_GPI_INT(GPIO_22, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_23, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_24, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_25, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_26, NONE, DEEP, OFF), + PAD_CFG_GPO(GPIO_27, 1, DEEP), + PAD_CFG_GPI_INT(GPIO_28, 20K_PU, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_29, 20K_PU, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_30, 20K_PU, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_31, 20K_PU, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_32, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_33, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_34, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_35, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_GPO(GPIO_36, 1, DEEP), + PAD_CFG_NF_IOSSTATE(GPIO_37, 20K_PD, PWROK, NF1, TxLASTRxE), + PAD_CFG_NF(GPIO_38, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_39, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_40, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_41, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_42, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_43, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_44, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_45, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPIO_46, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_47, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_48, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_49, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_62, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_63, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_64, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_65, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_66, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_67, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_68, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_69, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_70, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_71, NONE, DEEP, OFF), + PAD_CFG_TERM_GPO(GPIO_72, 0, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPIO_73, 0, 20K_PD, DEEP), + PAD_CFG_NF_IOSSTATE(TCK, 20K_PD, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(TRST_B, 20K_PD, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(TMS, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(TDI, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(CX_PMODE, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(CX_PREQ_B, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(JTAGX, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(CX_PRDY_B, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(TDO, 20K_PU, DEEP, NF1, IGNORE), + _PAD_CFG_STRUCT(CNV_BRI_DT, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(RX_DISABLE) | 1, + PAD_PULL(20K_PD) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(SAME)), + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, 1K_PU, DEEP), + PAD_CFG_GPO(CNV_RGI_DT, 1, DEEP), + /* CNV_RGI_RSP - RESERVED */ + PAD_CFG_GPI_INT(SVID0_ALERT_B, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(SVID0_DATA, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(SVID0_CLK, NONE, DEEP, OFF), - // *GPIO - _PAD_CFG_STRUCT(GPIO_2, 0x04000100, 0x00000000), + /* ******* GPIO Group NorthWest ******* */ + PAD_CFG_NF_IOSSTATE(GPIO_187, 20K_PU, DEEP, NF1, HIZCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_188, 20K_PU, DEEP, NF1, HIZCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_189, 2K_PU, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_190, 2K_PU, DEEP, NF1, TxLASTRxE), + PAD_CFG_GPI_INT(GPIO_191, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_192, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_193, 20K_PD, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_194, 20K_PD, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_195, 20K_PD, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_GPI_INT(GPIO_196, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_197, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_198, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_199, 20K_PU, DEEP, NF2, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_200, 20K_PU, DEEP, NF2, TxLASTRxE), + PAD_CFG_GPI_INT(GPIO_201, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_202, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_203, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_204, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(PMC_SPI_FS0, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(PMC_SPI_FS1, 20K_PU, DEEP, NF2, TxLASTRxE), + PAD_CFG_GPI_INT(PMC_SPI_FS2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(PMC_SPI_RXD, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(PMC_SPI_TXD, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(PMC_SPI_CLK, NONE, DEEP, OFF), + PAD_CFG_TERM_GPO(PMIC_PWRGOOD, 1, 1K_PU, DEEP), + PAD_CFG_GPI_INT(PMIC_RESET_B, NONE, DEEP, OFF), + PAD_CFG_TERM_GPO(GPIO_213, 1, 20K_PU, DEEP), + PAD_CFG_GPI_INT(GPIO_214, 20K_PU, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_215, 20K_PU, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(PMIC_THERMTRIP_B, 20K_PU, DEEP, NF1, TxLASTRxE), + PAD_CFG_TERM_GPO(PMIC_STDBY, 1, 20K_PD, DEEP), + PAD_CFG_NF_IOSSTATE(PROCHOT_B, 20K_PU, DEEP, NF1, HIZCRx1), + /* PMIC_I2C_SCL - RESERVED */ + /* PMIC_I2C_SDA - RESERVED */ + PAD_CFG_GPI_INT(GPIO_74, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_75, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_76, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_77, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_78, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_79, 20K_PD, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(GPIO_80, 20K_PD, DEEP, NF1, IGNORE), + PAD_CFG_NF(GPIO_81, 20K_PD, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_82, 20K_PD, DEEP, NF1, IGNORE), + PAD_CFG_NF(GPIO_83, 20K_PD, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_84, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF(GPIO_85, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPIO_86, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPIO_87, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_88, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPIO_89, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_90, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_91, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_92, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), + PAD_CFG_GPI_INT(GPIO_98, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), + PAD_CFG_GPI_INT(GPIO_101, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_102, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF(GPIO_104, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPIO_105, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_106, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_109, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_110, 20K_PU, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_111, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_112, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_113, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_116, 20K_PD, DEEP, NF1, HIZCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_117, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_118, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_119, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_120, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_121, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_122, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_123, 20K_PD, DEEP, NF1, TxLASTRxE), - // *GPIO - _PAD_CFG_STRUCT(GPIO_3, 0x04000100, 0x00000000), + /* ******* GPIO Group West ******* */ + PAD_CFG_NF(GPIO_124, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_125, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_126, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_127, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_128, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_129, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_130, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_131, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_132, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_133, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_134, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_135, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_136, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_137, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_138, 1K_PU, DEEP, NF1), + PAD_CFG_NF(GPIO_139, 1K_PU, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_146, 20K_PD, DEEP, NF2, IGNORE), + PAD_CFG_NF_IOSSTATE(GPIO_147, 20K_PD, DEEP, NF2, IGNORE), + PAD_CFG_NF_IOSSTATE(GPIO_148, 20K_PD, DEEP, NF2, IGNORE), + PAD_CFG_NF_IOSSTATE(GPIO_149, 20K_PD, DEEP, NF2, IGNORE), + PAD_CFG_NF(GPIO_150, 20K_PD, DEEP, NF2), + PAD_CFG_NF(GPIO_151, 20K_PD, DEEP, NF2), + PAD_CFG_NF(GPIO_152, 20K_PD, DEEP, NF2), + PAD_CFG_NF(GPIO_153, NONE, DEEP, NF2), + PAD_CFG_GPI_INT(GPIO_154, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(GPIO_155, 20K_PD, DEEP, NF2, IGNORE), + PAD_CFG_NF_IOSSTATE(GPIO_209, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_210, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_211, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_212, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(OSC_CLK_OUT_0, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(OSC_CLK_OUT_1, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(OSC_CLK_OUT_2, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(OSC_CLK_OUT_3, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_GPI_INT(OSC_CLK_OUT_4, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(PMU_AC_PRESENT, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(PMU_BATLOW_B, NONE, DEEP, OFF), + PAD_CFG_NF_IOSSTATE(PMU_PLTRST_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(PMU_PWRBTN_B, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(PMU_RESETBUTTON_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(PMU_SLP_S3_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(PMU_SLP_S4_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(PMU_SUSCLK, NONE, DEEP, NF1, IGNORE), + _PAD_CFG_STRUCT(PMU_WAKE_B, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(RX_DISABLE) | 1, + PAD_PULL(20K_PU) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(SAME)), + PAD_CFG_NF_IOSSTATE(SUS_STAT_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_GPI_INT(SUSPWRDNACK, NONE, DEEP, OFF), - // *GPIO - _PAD_CFG_STRUCT(GPIO_4, 0x04000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_5, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_6, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_7, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_8, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_9, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_10, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_11, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_12, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_13, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_14, 0x44000102, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_15, 0x44000102, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_16, 0x40880102, 0x00024000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_17, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_18, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_19, 0x44000201, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_20, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_21, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_22, 0x44000102, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_23, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_24, 0x44000102, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_25, 0x44000102, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_26, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_28, 0x44000102, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_30, 0x44000102, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_31, 0x44000102, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_32, 0x44000102, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_33, 0x44000102, 0x00000000), - - // PWM0 - _PAD_CFG_STRUCT(GPIO_34, 0x44000400, 0x00001000), - - // PWM1 - _PAD_CFG_STRUCT(GPIO_35, 0x44000400, 0x00001000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_36, 0x44000201, 0x00000000), - - // PWM3 - _PAD_CFG_STRUCT(GPIO_37, 0x04000400, 0x00001000), - - // LPSS_UART0_RXD - _PAD_CFG_STRUCT(GPIO_38, 0x44000402, 0x00023100), - - // LPSS_UART0_TXD - _PAD_CFG_STRUCT(GPIO_39, 0x44000400, 0x00003100), - - // LPSS_UART0_RTS_N - _PAD_CFG_STRUCT(GPIO_40, 0x44000400, 0x00003100), - - // LPSS_UART0_CTS_N - _PAD_CFG_STRUCT(GPIO_41, 0x44000402, 0x00023100), - - // LPSS_UART1_RXD - _PAD_CFG_STRUCT(GPIO_42, 0x44000402, 0x00023100), - - // LPSS_UART1_TXD - _PAD_CFG_STRUCT(GPIO_43, 0x44000400, 0x0001f100), - - // LPSS_UART1_RTS_N - _PAD_CFG_STRUCT(GPIO_44, 0x44000400, 0x00003100), - - // LPSS_UART1_CTS_N - _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x0001c100), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_46, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_47, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_48, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_49, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_62, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_63, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_64, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_65, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_66, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_67, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_68, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_69, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_70, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_71, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_72, 0x44000200, 0x00001000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_73, 0x44000200, 0x00001000), - - // *JTAG_TCK - _PAD_CFG_STRUCT(TCK, 0x44000400, 0x00c3d000), - - // *JTAG_TRST_N - _PAD_CFG_STRUCT(TRST_B, 0x44000400, 0x00c3d000), - - // *JTAG_TMS - _PAD_CFG_STRUCT(TMS, 0x44000400, 0x00c3f000), - - // *JTAG_TDI - _PAD_CFG_STRUCT(TDI, 0x44000400, 0x00c3f000), - - // *JTAG_PMODE - _PAD_CFG_STRUCT(CX_PMODE, 0x44000400, 0x00c3c000), - - // *JTAG_PREQ_N - _PAD_CFG_STRUCT(CX_PREQ_B, 0x44000402, 0x00c3f000), - - // *JTAGX - _PAD_CFG_STRUCT(JTAGX, 0x44000402, 0x00c3f000), - - // *JTAG_PRDY_N - _PAD_CFG_STRUCT(CX_PRDY_B, 0x44000402, 0x0043f000), - - // *JTAG_TDO - _PAD_CFG_STRUCT(TDO, 0x44000400, 0x0043f000), - - // GPIO - _PAD_CFG_STRUCT(CNV_BRI_DT, 0x44000201, 0x0003d000), - - // GPIO - _PAD_CFG_STRUCT(CNV_BRI_RSP, 0x44000201, 0x00002400), - - // GPIO - _PAD_CFG_STRUCT(CNV_RGI_DT, 0x44000201, 0x00000000), - - // RESERVED -// _PAD_CFG_STRUCT(CNV_RGI_RSP, 0xffffffff, 0xffffffff), - - // GPIO - _PAD_CFG_STRUCT(SVID0_ALERT_B, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(SVID0_DATA, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(SVID0_CLK, 0x44000100, 0x00000000), - - - // ************************************ - // ******* GPIO Group NorthWest ******* - // ************************************ - // *DDI0_DDC_SDA - _PAD_CFG_STRUCT(GPIO_187, 0x44000400, 0x0001f000), - - // *DDI0_DDC_SCL - _PAD_CFG_STRUCT(GPIO_188, 0x44000400, 0x0001f000), - - // *DDI1_DDC_SDA - _PAD_CFG_STRUCT(GPIO_189, 0x44000400, 0x00002c00), - - // *DDI1_DDC_SCL - _PAD_CFG_STRUCT(GPIO_190, 0x44000400, 0x00002c00), - - // GPIO - _PAD_CFG_STRUCT(GPIO_191, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_192, 0x44000100, 0x00000000), - - // *PNL0_VDDEN - _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x00005000), - - // *PNL0_BKLTEN - _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x00005000), - - // *PNL0_BKLTCTL - _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x00005000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_196, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_197, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_198, 0x44000100, 0x00000000), - - // DDI1_HPD - _PAD_CFG_STRUCT(GPIO_199, 0x44000800, 0x00003000), - - // DDI0_HPD - _PAD_CFG_STRUCT(GPIO_200, 0x44000802, 0x00003000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_201, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_202, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_203, 0x44000102, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_204, 0x44000102, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_FS0, 0x44000102, 0x00000000), - - // DDI2_HPD - _PAD_CFG_STRUCT(PMC_SPI_FS1, 0x44000802, 0x00003000), - - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_FS2, 0x44000102, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_RXD, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_TXD, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_CLK, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x44000203, 0x00002400), - - // GPIO - _PAD_CFG_STRUCT(PMIC_RESET_B, 0x44000102, 0x0003c000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00003300), - - // GPIO - _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00003300), - - // *THERMTRIP_N - _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000), - - // GPIO - _PAD_CFG_STRUCT(PMIC_STDBY, 0x44000201, 0x00001000), - - // *PROCHOT_N - _PAD_CFG_STRUCT(PROCHOT_B, 0x44000402, 0x00023000), - - // RESERVED -// _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0xffffffff, 0xffffffff), - - // RESERVED -// _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0xffffffff, 0xffffffff), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_74, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_75, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_76, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_77, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_78, 0x44000100, 0x00000000), - - // AVS_DMIC_CLK_A1 - _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d000), - - // AVS_DMIC_CLK_B1 - _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d000), - - // AVS_DMIC_DATA_1 - _PAD_CFG_STRUCT(GPIO_81, 0x44000400, 0x00025200), - - // AVS_DMIC_CLK_AB2 - _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d000), - - // AVS_DMIC_DATA_2 - _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x00025200), - - // AVS_I2S2_MCLK - _PAD_CFG_STRUCT(GPIO_84, 0x44000400, 0x00001000), - - // AVS_I2S2_BCLK - _PAD_CFG_STRUCT(GPIO_85, 0x44000400, 0x0001d200), - - // AVS_I2S2_WS_SYNC - _PAD_CFG_STRUCT(GPIO_86, 0x44000402, 0x0001d200), - - // AVS_I2S2_SDI - _PAD_CFG_STRUCT(GPIO_87, 0x44000402, 0x0001f200), - - // AVS_I2S2_SDO - _PAD_CFG_STRUCT(GPIO_88, 0x44000400, 0x0001c200), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_89, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_90, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_91, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_92, 0x44000100, 0x00000000), - - // *FST_SPI_CS0_N - _PAD_CFG_STRUCT(GPIO_97, 0x44000402, 0x0003fc00), - - // GPIO - _PAD_CFG_STRUCT(GPIO_98, 0x44000100, 0x00000000), - - // *FST_SPI_MOSI_IO0 - _PAD_CFG_STRUCT(GPIO_99, 0x44000400, 0x0003fc00), - - // *FST_SPI_MISO_IO1 - _PAD_CFG_STRUCT(GPIO_100, 0x44000402, 0x0003fc00), - - // GPIO - _PAD_CFG_STRUCT(GPIO_101, 0x44000100, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_102, 0x44000100, 0x00000000), - - // *FST_SPI_CLK - _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003fc00), - - // *n/a - _PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x44000400, 0x0003c000), - - // SIO_SPI_0_CLK - _PAD_CFG_STRUCT(GPIO_104, 0x44000400, 0x0001d200), - - // SIO_SPI_0_FS0 - _PAD_CFG_STRUCT(GPIO_105, 0x44000400, 0x0001f200), - - // SIO_SPI_0_FS1 - _PAD_CFG_STRUCT(GPIO_106, 0x44000400, 0x0001f200), - - // SIO_SPI_0_RXD - _PAD_CFG_STRUCT(GPIO_109, 0x44000402, 0x0001f200), - - // SIO_SPI_0_TXD - _PAD_CFG_STRUCT(GPIO_110, 0x44000400, 0x0001f200), - - // SIO_SPI_1_CLK - _PAD_CFG_STRUCT(GPIO_111, 0x44000400, 0x00001000), - - // SIO_SPI_1_FS0 - _PAD_CFG_STRUCT(GPIO_112, 0x44000400, 0x00001000), - - // SIO_SPI_1_FS1 - _PAD_CFG_STRUCT(GPIO_113, 0x44000400, 0x00001000), - - // SIO_SPI_1_RXD - _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0001d000), - - // SIO_SPI_1_TXD - _PAD_CFG_STRUCT(GPIO_117, 0x44000400, 0x00001000), - - // SIO_SPI_2_CLK - _PAD_CFG_STRUCT(GPIO_118, 0x44000400, 0x00001000), - - // SIO_SPI_2_FS0 - _PAD_CFG_STRUCT(GPIO_119, 0x44000400, 0x00001000), - - // SIO_SPI_2_FS1 - _PAD_CFG_STRUCT(GPIO_120, 0x44000400, 0x00001000), - - // SIO_SPI_2_FS2 - _PAD_CFG_STRUCT(GPIO_121, 0x44000400, 0x00001000), - - // SIO_SPI_2_RXD - _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00001000), - - // SIO_SPI_2_TXD - _PAD_CFG_STRUCT(GPIO_123, 0x44000400, 0x00001000), - - - // ******************************* - // ******* GPIO Group West ******* - // ******************************* - // LPSS_I2C0_SDA - _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x00012700), - - // LPSS_I2C0_SCL - _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x00012700), - - // LPSS_I2C1_SDA - _PAD_CFG_STRUCT(GPIO_126, 0x44000402, 0x00012700), - - // LPSS_I2C1_SCL - _PAD_CFG_STRUCT(GPIO_127, 0x44000402, 0x00012700), - - // LPSS_I2C2_SDA - _PAD_CFG_STRUCT(GPIO_128, 0x44000402, 0x00012700), - - // LPSS_I2C2_SCL - _PAD_CFG_STRUCT(GPIO_129, 0x44000402, 0x00012700), - - // LPSS_I2C3_SDA - _PAD_CFG_STRUCT(GPIO_130, 0x44000402, 0x00012700), - - // LPSS_I2C3_SCL - _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x00012700), - - // LPSS_I2C4_SDA - _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x00012700), - - // LPSS_I2C4_SCL - _PAD_CFG_STRUCT(GPIO_133, 0x44000402, 0x00012700), - - // LPSS_I2C5_SDA - _PAD_CFG_STRUCT(GPIO_134, 0x44000402, 0x0001f200), - - // LPSS_I2C5_SCL - _PAD_CFG_STRUCT(GPIO_135, 0x44000402, 0x0001f200), - - // LPSS_I2C6_SDA - _PAD_CFG_STRUCT(GPIO_136, 0x44000402, 0x0001f200), - - // LPSS_I2C6_SCL - _PAD_CFG_STRUCT(GPIO_137, 0x44000402, 0x0001f200), - - // LPSS_I2C7_SDA - _PAD_CFG_STRUCT(GPIO_138, 0x44000402, 0x00006700), - - // LPSS_I2C7_SCL - _PAD_CFG_STRUCT(GPIO_139, 0x44000402, 0x00006700), - - // AVS_I2S6_BCLK - _PAD_CFG_STRUCT(GPIO_146, 0x44000800, 0x0003d000), - - // AVS_I2S6_WS_SYNC - _PAD_CFG_STRUCT(GPIO_147, 0x44000800, 0x0003d000), - - // AVS_I2S6_SDI - _PAD_CFG_STRUCT(GPIO_148, 0x44000802, 0x0003d000), - - // AVS_I2S6_SDO - _PAD_CFG_STRUCT(GPIO_149, 0x44000800, 0x0003d000), - - // AVS_I2S5_BCLK - _PAD_CFG_STRUCT(GPIO_150, 0x44000800, 0x0001d200), - - // AVS_I2S5_WS_SYNC - _PAD_CFG_STRUCT(GPIO_151, 0x44000800, 0x0001d200), - - // AVS_I2S5_SDI - _PAD_CFG_STRUCT(GPIO_152, 0x44000802, 0x0001d200), - - // AVS_I2S5_SDO - _PAD_CFG_STRUCT(GPIO_153, 0x44000800, 0x0001c200), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_154, 0x44000102, 0x00000000), - - // SPKR - _PAD_CFG_STRUCT(GPIO_155, 0x44000800, 0x0003d000), - - // *PCIE_CLKREQ0_N - _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x00001000), - - // *PCIE_CLKREQ1_N - _PAD_CFG_STRUCT(GPIO_210, 0x44000400, 0x00001000), - - // *PCIE_CLKREQ2_N - _PAD_CFG_STRUCT(GPIO_211, 0x44000400, 0x00001000), - - // *PCIE_CLKREQ3_N - _PAD_CFG_STRUCT(GPIO_212, 0x44000400, 0x00001000), - - // *OSC_CLK_OUT_0 - _PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x44000400, 0x00001000), - - // *OSC_CLK_OUT_1 - _PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x44000400, 0x00001000), - - // *OSC_CLK_OUT_2 - _PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x44000400, 0x00001000), - - // *OSC_CLK_OUT_3 - _PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x44000400, 0x00001000), - - // GPIO - _PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x44000100, 0x00000000), - - // *GPIO - _PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x44000102, 0x00000000), - - // GPIO - _PAD_CFG_STRUCT(PMU_BATLOW_B, 0x44000102, 0x00000000), - - // *PMU_PLTRST_N - _PAD_CFG_STRUCT(PMU_PLTRST_B, 0x44000400, 0x0003c000), - - // *PMU_PWRBTN_N - _PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x44000402, 0x0003f000), - - // *PMU_RSTBTN_N - _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x44000402, 0x0003c000), - - // *PMU_SLP_S0_N - _PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x44000400, 0x0003c000), - - // *PMU_SLP_S3_N - _PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x44000400, 0x0003c000), - - // *PMU_SLP_S4_N - _PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x44000400, 0x0003c000), - - // *PMU_SUSCLK - _PAD_CFG_STRUCT(PMU_SUSCLK, 0x44000400, 0x0003c000), - - // *GPIO - _PAD_CFG_STRUCT(PMU_WAKE_B, 0x44000201, 0x0003f000), - - // *SUS_STAT_B - _PAD_CFG_STRUCT(SUS_STAT_B, 0x44000400, 0x0003c000), - - // GPIO - _PAD_CFG_STRUCT(SUSPWRDNACK, 0x44000102, 0x00000000), - - - // ************************************ - // ******* GPIO Group SouthWest ******* - // ************************************ - // PCIE_WAKE0_N - _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00000000), - - // PCIE_WAKE1_N - _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00000000), - - // PCIE_WAKE2_N - _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00000000), - - // PCIE_WAKE3_N - _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00000000), - - // *EMMC_CLK - _PAD_CFG_STRUCT(GPIO_156, 0x44000402, 0x00005000), - - // *EMMC_D0 - _PAD_CFG_STRUCT(GPIO_157, 0x44000402, 0x00023000), - - // *EMMC_D1 - _PAD_CFG_STRUCT(GPIO_158, 0x44000402, 0x00023000), - - // *EMMC_D2 - _PAD_CFG_STRUCT(GPIO_159, 0x44000402, 0x00023000), - - // *EMMC_D3 - _PAD_CFG_STRUCT(GPIO_160, 0x44000402, 0x00023000), - - // *EMMC_D4 - _PAD_CFG_STRUCT(GPIO_161, 0x44000402, 0x00023000), - - // *EMMC_D5 - _PAD_CFG_STRUCT(GPIO_162, 0x44000402, 0x00023000), - - // *EMMC_D6 - _PAD_CFG_STRUCT(GPIO_163, 0x44000402, 0x00023000), - - // *EMMC_D7 - _PAD_CFG_STRUCT(GPIO_164, 0x44000402, 0x00023000), - - // *EMMC_CMD - _PAD_CFG_STRUCT(GPIO_165, 0x44000402, 0x00023000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_166, 0x44000300, 0x00001000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_167, 0x44000102, 0x00023000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_168, 0x44000100, 0x00023000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_169, 0x44000200, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_170, 0x44000201, 0x00003000), - - // *GPIO - _PAD_CFG_STRUCT(GPIO_171, 0x44000201, 0x00003000), - - // SDCARD_CLK - _PAD_CFG_STRUCT(GPIO_172, 0x44000400, 0x00021100), - - // n/a - _PAD_CFG_STRUCT(GPIO_179, 0x44000400, 0x00001000), - - // SDCARD_D0 - _PAD_CFG_STRUCT(GPIO_173, 0x44000402, 0x00023100), - - // SDCARD_D1 - _PAD_CFG_STRUCT(GPIO_174, 0x44000402, 0x00023000), - - // SDCARD_D2 - _PAD_CFG_STRUCT(GPIO_175, 0x44000402, 0x00023000), - - // SDCARD_D3 - _PAD_CFG_STRUCT(GPIO_176, 0x44000402, 0x00023000), - - // SDCARD_CD_B - _PAD_CFG_STRUCT(GPIO_177, 0x44000402, 0x00003000), - - // SDCARD_CMD - _PAD_CFG_STRUCT(GPIO_178, 0x44000402, 0x00023100), - - // SDCARD_LVL_WP - _PAD_CFG_STRUCT(GPIO_186, 0x44000402, 0x00003000), - - // *EMMC_RCLK - _PAD_CFG_STRUCT(GPIO_182, 0x44000400, 0x0001d000), - - // GPIO - _PAD_CFG_STRUCT(GPIO_183, 0x44000200, 0x00001000), - - // SMB_ALERT_N - _PAD_CFG_STRUCT(SMB_ALERTB, 0x44000402, 0x0003f000), - - // SMB_CLK - _PAD_CFG_STRUCT(SMB_CLK, 0x44000402, 0x0003f000), - - // SMB_DATA - _PAD_CFG_STRUCT(SMB_DATA, 0x44000402, 0x0003f000), - - // LPC_ILB_SERIRQ - _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x44000402, 0x0003f000), - - // LPC_CLKOUT0 - _PAD_CFG_STRUCT(LPC_CLKOUT0, 0x44000400, 0x00020100), - - // LPC_CLKOUT1 - _PAD_CFG_STRUCT(LPC_CLKOUT1, 0x44000400, 0x00020100), - - // LPC_AD0 - _PAD_CFG_STRUCT(LPC_AD0, 0x44000402, 0x00023100), - - // LPC_AD1 - _PAD_CFG_STRUCT(LPC_AD1, 0x44000402, 0x00023100), - - // LPC_AD2 - _PAD_CFG_STRUCT(LPC_AD2, 0x44000402, 0x00023100), - - // LPC_AD3 - _PAD_CFG_STRUCT(LPC_AD3, 0x44000402, 0x00023100), - - // LPC_CLKRUNB - _PAD_CFG_STRUCT(LPC_CLKRUNB, 0x44000400, 0x00023100), - - // LPC_FRAMEB - _PAD_CFG_STRUCT(LPC_FRAMEB, 0x44000400, 0x00023100), + /* ******* GPIO Group SouthWest ******* */ + PAD_CFG_NF_IOSSTATE(GPIO_205, NONE, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_206, NONE, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_207, NONE, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_208, NONE, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_156, 20K_PD, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_157, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_158, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_159, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_160, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_161, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_162, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_163, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_164, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_165, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_NC(GPIO_166, 20K_PD), + PAD_CFG_GPI_INT(GPIO_167, 20K_PU, DEEP, OFF), + PAD_CFG_GPI_INT(GPIO_168, 20K_PU, DEEP, OFF), + PAD_CFG_TERM_GPO(GPIO_169, 0, 20K_PU, DEEP), + PAD_CFG_TERM_GPO(GPIO_170, 1, 20K_PU, DEEP), + PAD_CFG_TERM_GPO(GPIO_171, 1, 20K_PU, DEEP), + PAD_CFG_NF(GPIO_172, 20K_PD, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_179, 20K_PD, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF(GPIO_173, 20K_PU, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_174, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_175, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_176, 20K_PU, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_177, 20K_PU, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF(GPIO_178, 20K_PU, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_186, 20K_PU, DEEP, NF1, TxLASTRxE), + PAD_CFG_NF_IOSSTATE(GPIO_182, 20K_PD, DEEP, NF1, HIZCRx0), + PAD_CFG_TERM_GPO(GPIO_183, 0, 20K_PD, DEEP), + PAD_CFG_NF_IOSSTATE(SMB_ALERTB, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(SMB_CLK, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(SMB_DATA, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF_IOSSTATE(LPC_ILB_SERIRQ, 20K_PU, DEEP, NF1, IGNORE), + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, 20K_PU, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, 20K_PU, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, 20K_PU, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, 20K_PU, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, 20K_PU, DEEP, NF1), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I266ec6fa10a9691a7b7d3cd6f2792624e8bd53d5 Gerrit-Change-Number: 39765 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020