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Change in coreboot[master]: mb/asrock/h110m: Relocate devicetree FSP settings
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43919 ) Change subject: mb/asrock/h110m: Relocate devicetree FSP settings ...................................................................... mb/asrock/h110m: Relocate devicetree FSP settings Some settings are suspicious, and have been annotated with FIXMEs. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 77 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/43919/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 977fa29..b299b41 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -28,17 +28,10 @@ register "dptf_enable" = "1" # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "SkipExtGfxScan" = "0" register "PrimaryDisplay" = "Display_PEG" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "PchHdaVcType" = "Vc1" @@ -125,8 +118,6 @@ .voltage_limit = 1520 \ }" - register "EnableLan" = "0" - # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" @@ -142,6 +133,7 @@ register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" @@ -153,25 +145,6 @@ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" - # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - # SATA4 and SATA5 are located in the lower right corner of the board, - # but they are not populated. This is because the same PCB is used to - # make boards with better PCHs, which can have up to six SATA ports. - # However, the H110 PCH only has four SATA ports, which explains why - # two connectors are missing. - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - # PCH UART, SPI, I2C register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ @@ -187,55 +160,6 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Disable CLKREQ#, since onboard LAN is always present - register "PcieRpClkReqSupport[5]" = "0" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - # PL2 override 91W register "power_limits_config" = "{ .tdp_pl2_override = 91, @@ -253,11 +177,19 @@ end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + register "Peg0MaxLinkWidth" = "Peg0_x16" + + # Configure PCIe clockgen in PCH + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end - device pci 04.0 on end # Thermal Subsystem + device pci 04.0 on # Thermal Subsystem + register "Device4Enable" = "1" + end device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 @@ -270,8 +202,11 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -279,6 +214,23 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA subsystemid 0x1849 0xa102 + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + # SATA4 and SATA5 are located in the lower right corner of the board, + # but they are not populated. This is because the same PCB is used to + # make boards with better PCHs, which can have up to six SATA ports. + # However, the H110 PCH only has four SATA ports, which explains why + # two connectors are missing. + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" end device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 @@ -287,9 +239,33 @@ device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 on # PCI Express Port 5 - PCIE slot + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" + register "PcieRpHotPlug[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 - Onboard LAN + register "PcieRpEnable[5]" = "1" + + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device pci 1c.6 on # PCI Express Port 7 - PCIE slot + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "3" + register "PcieRpHotPlug[6]" = "1" + end device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -299,10 +275,15 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC + device pci 1e.4 off # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end + device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 chip superio/common @@ -412,9 +393,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/43919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Gerrit-Change-Number: 43919 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Add Generic Non-Core register definitions
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43740 ) Change subject: nb/intel/ironlake: Add Generic Non-Core register definitions ...................................................................... nb/intel/ironlake: Add Generic Non-Core register definitions Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 3 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/43740/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 24657d6..fa89bd9 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -43,7 +43,7 @@ /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000); + pci_update_config32(QPI_NON_CORE, DESIRED_CORES, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 4f9db5b..325de5b 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -52,6 +52,10 @@ */ #define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) +#define MAX_RTIDS 0x60 +#define DESIRED_CORES 0x80 +#define MIRROR_PORT_CTL 0xd0 + /* * SAD - System Address Decoder */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 6c3a499..a3dc605 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3951,8 +3951,8 @@ pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! - pci_read_config32(QPI_NON_CORE, 0xd0); // !!!! - pci_write_config32(QPI_NON_CORE, 0xd0, 0x180); + pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL); // !!!! + pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180); gav(MCHBAR32(0x1af0)); // !!!! gav(MCHBAR32(0x1af0)); // !!!! MCHBAR32(0x1af0) = 0x1f020003; @@ -4221,7 +4221,7 @@ MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! - pci_write_config32(QPI_NON_CORE, 0x60, 0x20220); + pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! MCHBAR16(0x2c00); // !!!! -- To view, visit https://review.coreboot.org/c/coreboot/+/43740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511 Gerrit-Change-Number: 43740 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add Generic Non-Core PCI device definition
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43739 ) Change subject: nb/intel/ironlake: Add Generic Non-Core PCI device definition ...................................................................... nb/intel/ironlake: Add Generic Non-Core PCI device definition Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 3 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43739/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 2154478..24657d6 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -43,7 +43,7 @@ /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000); + pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 06e0771..4f9db5b 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -48,6 +48,11 @@ #include "hostbridge_regs.h" /* + * Generic Non-Core Registers + */ +#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) + +/* * SAD - System Address Decoder */ #define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index b35d4c7..6c3a499 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3951,8 +3951,8 @@ pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! - pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! - pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); + pci_read_config32(QPI_NON_CORE, 0xd0); // !!!! + pci_write_config32(QPI_NON_CORE, 0xd0, 0x180); gav(MCHBAR32(0x1af0)); // !!!! gav(MCHBAR32(0x1af0)); // !!!! MCHBAR32(0x1af0) = 0x1f020003; @@ -4221,7 +4221,7 @@ MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! - pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); + pci_write_config32(QPI_NON_CORE, 0x60, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! MCHBAR16(0x2c00); // !!!! -- To view, visit https://review.coreboot.org/c/coreboot/+/43739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd Gerrit-Change-Number: 43739 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add QPI Physical Layer registers
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43738 ) Change subject: nb/intel/ironlake: Add QPI Physical Layer registers ...................................................................... nb/intel/ironlake: Add QPI Physical Layer registers Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I44db564c757647f493e92d35602178ef8b722517 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 2 files changed, 23 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/43738/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index d09cccc..06e0771 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -75,6 +75,16 @@ */ #define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) +#define QPI_PLL_STATUS 0x50 +#define QPI_PLL_RATIO 0x54 +#define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */ +#define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */ +#define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */ +#define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */ +#define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */ +#define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */ +#define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 100e1e8..b35d4c7 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3878,8 +3878,8 @@ MCHBAR32_OR(0x1890, 0x2000000); MCHBAR32_OR(0x18b4, 0x8000); - gav(pci_read_config32(QPI_PHY_0, 0x50)); // !!!! - pci_write_config8(QPI_PHY_0, 0x54, 0x12); + gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!! + pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12); gav(MCHBAR16(0x2c10)); MCHBAR16(0x2c10) = 0x412; @@ -3889,8 +3889,8 @@ gav(MCHBAR8(0x2ca8)); // !!!! MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080); - pci_read_config32(QPI_PHY_0, 0x6c); // !!!! - pci_write_config32(QPI_PHY_0, 0x6c, 0x40a0a0); + pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!! + pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0); gav(MCHBAR32(0x1c04)); // !!!! gav(MCHBAR32(0x1804)); // !!!! @@ -3900,16 +3900,16 @@ MCHBAR32(0x18d8) = 0x120000; MCHBAR32(0x18dc) = 0x30a484a; - pci_write_config32(QPI_PHY_0, 0xe0, 0x0); - pci_write_config32(QPI_PHY_0, 0xf4, 0x9444a); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a); MCHBAR32(0x18d8) = 0x40000; MCHBAR32(0x18dc) = 0xb000000; - pci_write_config32(QPI_PHY_0, 0xe0, 0x60000); - pci_write_config32(QPI_PHY_0, 0xf4, 0x0); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x0); MCHBAR32(0x18d8) = 0x180000; MCHBAR32(0x18dc) = 0xc0000142; - pci_write_config32(QPI_PHY_0, 0xe0, 0x20000); - pci_write_config32(QPI_PHY_0, 0xf4, 0x142); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x20000); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x142); MCHBAR32(0x18d8) = 0x1e0000; gav(MCHBAR32(0x18dc)); // !!!! @@ -3921,7 +3921,7 @@ } MCHBAR32(0x188c) = 0x20bc09; - pci_write_config32(QPI_PHY_0, 0xd0, 0x40b0c09); + pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09); MCHBAR32(0x1a10) = 0x4200010e; MCHBAR32_OR(0x18b8, 0x200); gav(MCHBAR32(0x1918)); // !!!! @@ -3931,8 +3931,8 @@ MCHBAR32(0x18b8) = 0xe00; gav(MCHBAR32(0x182c)); // !!!! MCHBAR32(0x182c) = 0x10202; - gav(pci_read_config32(QPI_PHY_0, 0x94)); // !!!! - pci_write_config32(QPI_PHY_0, 0x94, 0x10202); + gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!! + pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202); MCHBAR32_AND(0x1a1c, 0x8fffffff); MCHBAR32_OR(0x1a70, 0x100000); -- To view, visit https://review.coreboot.org/c/coreboot/+/43738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44db564c757647f493e92d35602178ef8b722517 Gerrit-Change-Number: 43738 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add QPI Physical Layer device definition
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43737 ) Change subject: nb/intel/ironlake: Add QPI Physical Layer device definition ...................................................................... nb/intel/ironlake: Add QPI Physical Layer device definition Like the QPI Link device, there can be more of these devices on multi-socket platforms. So, name it Physical Layer 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 2 files changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/43737/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index aa2399f..d09cccc 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -70,6 +70,11 @@ #define QPI_QPILS 0x50 /* QPI Link Status */ #define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ +/* + * QPI Physical Layer 0 + */ +#define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 1223b5d..100e1e8 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3878,8 +3878,8 @@ MCHBAR32_OR(0x1890, 0x2000000); MCHBAR32_OR(0x18b4, 0x8000); - gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!! - pci_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12); + gav(pci_read_config32(QPI_PHY_0, 0x50)); // !!!! + pci_write_config8(QPI_PHY_0, 0x54, 0x12); gav(MCHBAR16(0x2c10)); MCHBAR16(0x2c10) = 0x412; @@ -3889,8 +3889,8 @@ gav(MCHBAR8(0x2ca8)); // !!!! MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080); - pci_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0); + pci_read_config32(QPI_PHY_0, 0x6c); // !!!! + pci_write_config32(QPI_PHY_0, 0x6c, 0x40a0a0); gav(MCHBAR32(0x1c04)); // !!!! gav(MCHBAR32(0x1804)); // !!!! @@ -3900,16 +3900,16 @@ MCHBAR32(0x18d8) = 0x120000; MCHBAR32(0x18dc) = 0x30a484a; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x0); - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x9444a); + pci_write_config32(QPI_PHY_0, 0xe0, 0x0); + pci_write_config32(QPI_PHY_0, 0xf4, 0x9444a); MCHBAR32(0x18d8) = 0x40000; MCHBAR32(0x18dc) = 0xb000000; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x60000); - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x0); + pci_write_config32(QPI_PHY_0, 0xe0, 0x60000); + pci_write_config32(QPI_PHY_0, 0xf4, 0x0); MCHBAR32(0x18d8) = 0x180000; MCHBAR32(0x18dc) = 0xc0000142; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x20000); - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142); + pci_write_config32(QPI_PHY_0, 0xe0, 0x20000); + pci_write_config32(QPI_PHY_0, 0xf4, 0x142); MCHBAR32(0x18d8) = 0x1e0000; gav(MCHBAR32(0x18dc)); // !!!! @@ -3921,7 +3921,7 @@ } MCHBAR32(0x188c) = 0x20bc09; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09); + pci_write_config32(QPI_PHY_0, 0xd0, 0x40b0c09); MCHBAR32(0x1a10) = 0x4200010e; MCHBAR32_OR(0x18b8, 0x200); gav(MCHBAR32(0x1918)); // !!!! @@ -3931,8 +3931,8 @@ MCHBAR32(0x18b8) = 0xe00; gav(MCHBAR32(0x182c)); // !!!! MCHBAR32(0x182c) = 0x10202; - gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202); + gav(pci_read_config32(QPI_PHY_0, 0x94)); // !!!! + pci_write_config32(QPI_PHY_0, 0x94, 0x10202); MCHBAR32_AND(0x1a1c, 0x8fffffff); MCHBAR32_OR(0x1a70, 0x100000); -- To view, visit https://review.coreboot.org/c/coreboot/+/43737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e Gerrit-Change-Number: 43737 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add QPI Link register definitions
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43736 ) Change subject: nb/intel/ironlake: Add QPI Link register definitions ...................................................................... nb/intel/ironlake: Add QPI Link register definitions Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 2 files changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/43736/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index bd42f210..aa2399f 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -65,6 +65,11 @@ */ #define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) +#define QPI_QPILCP 0x40 /* QPI Link Capability */ +#define QPI_QPILCL 0x48 /* QPI Link Control */ +#define QPI_QPILS 0x50 /* QPI Link Status */ +#define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index d5c2f62..1223b5d 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3946,11 +3946,11 @@ MCHBAR8_OR(0x2ca8, 1); // guess } - pci_read_config32(QPI_LINK_0, 0x048); // !!!! - pci_write_config32(QPI_LINK_0, 0x048, 0x140000); - pci_read_config32(QPI_LINK_0, 0x058); // !!!! - pci_write_config32(QPI_LINK_0, 0x058, 0x64555); - pci_read_config32(QPI_LINK_0, 0x058); // !!!! + pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!! + pci_write_config32(QPI_LINK_0, QPI_QPILCL, 0x140000); + pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! + pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); + pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); gav(MCHBAR32(0x1af0)); // !!!! -- To view, visit https://review.coreboot.org/c/coreboot/+/43736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e Gerrit-Change-Number: 43736 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add definition for QPI Link PCI device
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43735 ) Change subject: nb/intel/ironlake: Add definition for QPI Link PCI device ...................................................................... nb/intel/ironlake: Add definition for QPI Link PCI device On multi-socket platforms, there can be two QPI buses, each with its own PCI device. We only have one QPI link on Arrandale, though. In case support for multi-socket processors ever gets added, name it Link 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 2 files changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/43735/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index fa59565..bd42f210 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -60,6 +60,11 @@ #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ +/* + * QPI Link 0 + */ +#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 9a25411..d5c2f62 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3946,11 +3946,11 @@ MCHBAR8_OR(0x2ca8, 1); // guess } - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! + pci_read_config32(QPI_LINK_0, 0x048); // !!!! + pci_write_config32(QPI_LINK_0, 0x048, 0x140000); + pci_read_config32(QPI_LINK_0, 0x058); // !!!! + pci_write_config32(QPI_LINK_0, 0x058, 0x64555); + pci_read_config32(QPI_LINK_0, 0x058); // !!!! pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); gav(MCHBAR32(0x1af0)); // !!!! -- To view, visit https://review.coreboot.org/c/coreboot/+/43735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Gerrit-Change-Number: 43735 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add SAD DRAM register definitions
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43734 ) Change subject: nb/intel/ironlake: Add SAD DRAM register definitions ...................................................................... nb/intel/ironlake: Add SAD DRAM register definitions Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/43734/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index afd3082..fa59565 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -57,6 +57,9 @@ #define SAD_PCIEXBAR 0x50 +#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ +#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 1017be4..9a25411 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1337,9 +1337,9 @@ MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); for (i = 0; i < 8; i++) { - pci_write_config32(QPI_SAD, 0x80 + 4 * i, + pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (info->total_memory_mb - 64) | !i | 2); - pci_write_config32(QPI_SAD, 0xc0 + 4 * i, 0); + pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); } } @@ -1452,10 +1452,10 @@ memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = MAX(current_limit, memory_map[i] & ~1); - pci_write_config32(QPI_SAD, 4 * i + 0x80, + pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pci_write_config32(QPI_SAD, 4 * i + 0xc0, 0); + pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/43734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6 Gerrit-Change-Number: 43734 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Correct PCIEXBAR definition
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43733 ) Change subject: nb/intel/ironlake: Correct PCIEXBAR definition ...................................................................... nb/intel/ironlake: Correct PCIEXBAR definition This register resides within the SAD's config space, and is 64-bit. Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/ironlake.h 4 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43733/1 diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 1fa7267..c954086 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ u32 pciexbar_reg; int max_buses; - pciexbar_reg = pci_read_config32(QPI_SAD, 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 50e7adb..89eb813 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -6,6 +6,6 @@ void bootblock_early_northbridge_init(void) { - pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(QPI_SAD, 0x54, 0); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0); } diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index b835736..a681734 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -11,7 +11,6 @@ #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0) -#define PCIEXBAR 0x60 #define DMIBAR 0x68 #define LAC 0x87 /* Legacy Access Control */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index dd8de97..afd3082 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -55,6 +55,8 @@ #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ +#define SAD_PCIEXBAR 0x50 + /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Gerrit-Change-Number: 43733 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Add definition for SAD PCI device
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43732 ) Change subject: nb/intel/ironlake: Add definition for SAD PCI device ...................................................................... nb/intel/ironlake: Add definition for SAD PCI device Let's hope this cheers up the poor System Address Decoder device. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/ironlake/smi.c 6 files changed, 20 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43732/1 diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 7289e92..1fa7267 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ u32 pciexbar_reg; int max_buses; - pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, 0x50); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index d40b0b5..50e7adb 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -2,9 +2,10 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include "ironlake.h" void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); + pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, 0x54, 0); } diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b68d954..2154478 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -25,13 +25,13 @@ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30); + pci_write_config8(QPI_SAD, QPD0F1_PAM(1), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(2), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(3), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(4), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(5), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(6), 0x33); printk(BIOS_DEBUG, " done.\n"); } diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 5a1d52e..dd8de97 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -48,8 +48,10 @@ #include "hostbridge_regs.h" /* - * QPI D0:F1 + * SAD - System Address Decoder */ +#define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) + #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 3d27762..1017be4 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1337,9 +1337,9 @@ MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); for (i = 0; i < 8; i++) { - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, + pci_write_config32(QPI_SAD, 0x80 + 4 * i, (info->total_memory_mb - 64) | !i | 2); - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); + pci_write_config32(QPI_SAD, 0xc0 + 4 * i, 0); } } @@ -1412,7 +1412,7 @@ memory_map[2] = touud | 1; quickpath_reserved = 0; - u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); + u32 t = pci_read_config32(QPI_SAD, 0x68); gav(t); @@ -1452,10 +1452,10 @@ memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = MAX(current_limit, memory_map[i] & ~1); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, + pci_write_config32(QPI_SAD, 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); + pci_write_config32(QPI_SAD, 4 * i + 0xc0, 0); } } diff --git a/src/northbridge/intel/ironlake/smi.c b/src/northbridge/intel/ironlake/smi.c index 9ffcb99..0604d13 100644 --- a/src/northbridge/intel/ironlake/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -11,5 +11,5 @@ void northbridge_write_smram(u8 smram) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_write_config8(QPI_SAD, QPD0F1_SMRAM, smram); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1 Gerrit-Change-Number: 43732 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020